IEICE TRANSACTIONS on Electronics
Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI
Summary :
This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E83-C No.2 pp.170-178
- Publication Date
- 2000/02/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-Power High-Speed CMOS LSI Technologies)
- Category
Authors
Mitsuo IKEDA
Toshio KONDO
Koyo NITTA
Kazuhito SUGURI
Takeshi YOSHITOME
Toshihiro MINAMI
Jiro NAGANUMA
Takeshi OGURA
Keyword
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Mitsuo IKEDA, Toshio KONDO, Koyo NITTA, Kazuhito SUGURI, Takeshi YOSHITOME, Toshihiro MINAMI, Jiro NAGANUMA, Takeshi OGURA, "Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 2, pp. 170-178, February 2000, doi: .
Abstract: This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_2_170/_p
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@ARTICLE{e83-c_2_170,
author={Mitsuo IKEDA, Toshio KONDO, Koyo NITTA, Kazuhito SUGURI, Takeshi YOSHITOME, Toshihiro MINAMI, Jiro NAGANUMA, Takeshi OGURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI},
year={2000},
volume={E83-C},
number={2},
pages={170-178},
abstract={This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - Three-Layer Cooperative Architecture for MPEG-2 Video Encoder LSI
T2 - IEICE TRANSACTIONS on Electronics
SP - 170
EP - 178
AU - Mitsuo IKEDA
AU - Toshio KONDO
AU - Koyo NITTA
AU - Kazuhito SUGURI
AU - Takeshi YOSHITOME
AU - Toshihiro MINAMI
AU - Jiro NAGANUMA
AU - Takeshi OGURA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2000
AB - This paper presents an architecture for a single-chip MPEG-2 video encoder and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in the 0.25-µm four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.
ER -
English
