IEICE TRANSACTIONS on Electronics
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
Summary :
This paper proposes an all-digital process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. The proposed circuit has been fabricated in 65 nm CMOS process and the measurement results demonstrate that we can monitor the PMOS and NMOS variabilities independently using the proposed monitoring circuit. The proposed monitoring technique is suitable not only for the on-chip process variability monitoring but also for the in-field monitoring of aging effects such as negative/positive bias instability (NBTI/PBTI).
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E94-C No.4 pp.487-494
- Publication Date
- 2011/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E94.C.487
- Type of Manuscript
- Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
- Category
Authors
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Tetsuya IIZUKA, Jaehyun JEONG, Toru NAKURA, Makoto IKEDA, Kunihiro ASADA, "All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter" in IEICE TRANSACTIONS on Electronics,
vol. E94-C, no. 4, pp. 487-494, April 2011, doi: 10.1587/transele.E94.C.487.
Abstract: This paper proposes an all-digital process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. The proposed circuit has been fabricated in 65 nm CMOS process and the measurement results demonstrate that we can monitor the PMOS and NMOS variabilities independently using the proposed monitoring circuit. The proposed monitoring technique is suitable not only for the on-chip process variability monitoring but also for the in-field monitoring of aging effects such as negative/positive bias instability (NBTI/PBTI).
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E94.C.487/_p
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@ARTICLE{e94-c_4_487,
author={Tetsuya IIZUKA, Jaehyun JEONG, Toru NAKURA, Makoto IKEDA, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter},
year={2011},
volume={E94-C},
number={4},
pages={487-494},
abstract={This paper proposes an all-digital process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. The proposed circuit has been fabricated in 65 nm CMOS process and the measurement results demonstrate that we can monitor the PMOS and NMOS variabilities independently using the proposed monitoring circuit. The proposed monitoring technique is suitable not only for the on-chip process variability monitoring but also for the in-field monitoring of aging effects such as negative/positive bias instability (NBTI/PBTI).},
keywords={},
doi={10.1587/transele.E94.C.487},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter
T2 - IEICE TRANSACTIONS on Electronics
SP - 487
EP - 494
AU - Tetsuya IIZUKA
AU - Jaehyun JEONG
AU - Toru NAKURA
AU - Makoto IKEDA
AU - Kunihiro ASADA
PY - 2011
DO - 10.1587/transele.E94.C.487
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E94-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2011
AB - This paper proposes an all-digital process variability monitor which utilizes a simple buffer ring with a pulse counter. The proposed circuit monitors the process variability according to a count number of a single pulse which propagates on the buffer ring and a fixed logic level after the pulse vanishes. The proposed circuit has been fabricated in 65 nm CMOS process and the measurement results demonstrate that we can monitor the PMOS and NMOS variabilities independently using the proposed monitoring circuit. The proposed monitoring technique is suitable not only for the on-chip process variability monitoring but also for the in-field monitoring of aging effects such as negative/positive bias instability (NBTI/PBTI).
ER -
English
