This paper proposes a sub-ps resolution TDC utilizing a differential pulse-shrinking buffer ring. This scheme uses two differentially-operated pulse-shrinking inverters and the TDC resolution is finely controlled by the transistor size ratio between them. The proposed TDC realizes 9 bit, 580 fs resolution in a 0.18 µm CMOS technology with 0.04 mm2 area, and achieves DNL and INL of +0.8/-0.8LSB and +4.3/-4.0LSB, respectively, without linearity calibration. A power dissipation at 1.5 MS/s ranges from 10.8 to 12.6 mW depending on the input time intervals.
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Tetsuya IIZUKA, Satoshi MIURA, Ryota YAMAMOTO, Yutaka CHIBA, Shunichi KUBO, Kunihiro ASADA, "A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology" in IEICE TRANSACTIONS on Electronics,
vol. E95-C, no. 4, pp. 661-667, April 2012, doi: 10.1587/transele.E95.C.661.
Abstract: This paper proposes a sub-ps resolution TDC utilizing a differential pulse-shrinking buffer ring. This scheme uses two differentially-operated pulse-shrinking inverters and the TDC resolution is finely controlled by the transistor size ratio between them. The proposed TDC realizes 9 bit, 580 fs resolution in a 0.18 µm CMOS technology with 0.04 mm2 area, and achieves DNL and INL of +0.8/-0.8LSB and +4.3/-4.0LSB, respectively, without linearity calibration. A power dissipation at 1.5 MS/s ranges from 10.8 to 12.6 mW depending on the input time intervals.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E95.C.661/_p
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@ARTICLE{e95-c_4_661,
author={Tetsuya IIZUKA, Satoshi MIURA, Ryota YAMAMOTO, Yutaka CHIBA, Shunichi KUBO, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology},
year={2012},
volume={E95-C},
number={4},
pages={661-667},
abstract={This paper proposes a sub-ps resolution TDC utilizing a differential pulse-shrinking buffer ring. This scheme uses two differentially-operated pulse-shrinking inverters and the TDC resolution is finely controlled by the transistor size ratio between them. The proposed TDC realizes 9 bit, 580 fs resolution in a 0.18 µm CMOS technology with 0.04 mm2 area, and achieves DNL and INL of +0.8/-0.8LSB and +4.3/-4.0LSB, respectively, without linearity calibration. A power dissipation at 1.5 MS/s ranges from 10.8 to 12.6 mW depending on the input time intervals.},
keywords={},
doi={10.1587/transele.E95.C.661},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 661
EP - 667
AU - Tetsuya IIZUKA
AU - Satoshi MIURA
AU - Ryota YAMAMOTO
AU - Yutaka CHIBA
AU - Shunichi KUBO
AU - Kunihiro ASADA
PY - 2012
DO - 10.1587/transele.E95.C.661
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E95-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2012
AB - This paper proposes a sub-ps resolution TDC utilizing a differential pulse-shrinking buffer ring. This scheme uses two differentially-operated pulse-shrinking inverters and the TDC resolution is finely controlled by the transistor size ratio between them. The proposed TDC realizes 9 bit, 580 fs resolution in a 0.18 µm CMOS technology with 0.04 mm2 area, and achieves DNL and INL of +0.8/-0.8LSB and +4.3/-4.0LSB, respectively, without linearity calibration. A power dissipation at 1.5 MS/s ranges from 10.8 to 12.6 mW depending on the input time intervals.
ER -