IEICE TRANSACTIONS on Electronics
A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation
Summary :
A 60-GHz power amplifier (PA) with a reliability consideration for a hot-carrier-induced (HCI) degradation is presented. The supply voltage of the last stage of the PA (VPA) is dynamically controlled by an on-chip digitally-assisted low drop-out voltage regulator (LDO) to alleviate HCI effects. A physical model for estimation of HCI degradation of NMOSFETs is discussed and investigated for dynamic operation. The PA is fabricated in a standard 65-nm CMOS process with a core area of 0.21 mm2, which provides a saturation power of 10.1 dBm to 13.2 dBm with a peak power-added efficiency (PAE) of 8.1% to 15.0% for the supply voltage VPA which varies from 0.7 V to 1.0 V at 60 GHz, respectively.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E97-C No.8 pp.803-812
- Publication Date
- 2014/08/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E97.C.803
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
Authors
Rui WU
Tokyo Institute of Technology
Yuuki TSUKUI
Tokyo Institute of Technology
Ryo MINAMI
Tokyo Institute of Technology
Kenichi OKADA
Tokyo Institute of Technology
Akira MATSUZAWA
Tokyo Institute of Technology
Keyword
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Rui WU, Yuuki TSUKUI, Ryo MINAMI, Kenichi OKADA, Akira MATSUZAWA, "A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation" in IEICE TRANSACTIONS on Electronics,
vol. E97-C, no. 8, pp. 803-812, August 2014, doi: 10.1587/transele.E97.C.803.
Abstract: A 60-GHz power amplifier (PA) with a reliability consideration for a hot-carrier-induced (HCI) degradation is presented. The supply voltage of the last stage of the PA (VPA) is dynamically controlled by an on-chip digitally-assisted low drop-out voltage regulator (LDO) to alleviate HCI effects. A physical model for estimation of HCI degradation of NMOSFETs is discussed and investigated for dynamic operation. The PA is fabricated in a standard 65-nm CMOS process with a core area of 0.21 mm2, which provides a saturation power of 10.1 dBm to 13.2 dBm with a peak power-added efficiency (PAE) of 8.1% to 15.0% for the supply voltage VPA which varies from 0.7 V to 1.0 V at 60 GHz, respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.803/_p
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@ARTICLE{e97-c_8_803,
author={Rui WU, Yuuki TSUKUI, Ryo MINAMI, Kenichi OKADA, Akira MATSUZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation},
year={2014},
volume={E97-C},
number={8},
pages={803-812},
abstract={A 60-GHz power amplifier (PA) with a reliability consideration for a hot-carrier-induced (HCI) degradation is presented. The supply voltage of the last stage of the PA (VPA) is dynamically controlled by an on-chip digitally-assisted low drop-out voltage regulator (LDO) to alleviate HCI effects. A physical model for estimation of HCI degradation of NMOSFETs is discussed and investigated for dynamic operation. The PA is fabricated in a standard 65-nm CMOS process with a core area of 0.21 mm2, which provides a saturation power of 10.1 dBm to 13.2 dBm with a peak power-added efficiency (PAE) of 8.1% to 15.0% for the supply voltage VPA which varies from 0.7 V to 1.0 V at 60 GHz, respectively.},
keywords={},
doi={10.1587/transele.E97.C.803},
ISSN={1745-1353},
month={August},}
Copy
TY - JOUR
TI - A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation
T2 - IEICE TRANSACTIONS on Electronics
SP - 803
EP - 812
AU - Rui WU
AU - Yuuki TSUKUI
AU - Ryo MINAMI
AU - Kenichi OKADA
AU - Akira MATSUZAWA
PY - 2014
DO - 10.1587/transele.E97.C.803
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2014
AB - A 60-GHz power amplifier (PA) with a reliability consideration for a hot-carrier-induced (HCI) degradation is presented. The supply voltage of the last stage of the PA (VPA) is dynamically controlled by an on-chip digitally-assisted low drop-out voltage regulator (LDO) to alleviate HCI effects. A physical model for estimation of HCI degradation of NMOSFETs is discussed and investigated for dynamic operation. The PA is fabricated in a standard 65-nm CMOS process with a core area of 0.21 mm2, which provides a saturation power of 10.1 dBm to 13.2 dBm with a peak power-added efficiency (PAE) of 8.1% to 15.0% for the supply voltage VPA which varies from 0.7 V to 1.0 V at 60 GHz, respectively.
ER -
English
