IEICE TRANSACTIONS on Fundamentals
A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion
Summary :
This paper addresses the on-resistance (Ron) extraction of the DMOS based driver in Power IC designs. The proposed method can extract Ron of a driver from its layout data for the arbitrarily shaped metallization patterns. Such a driver is usually composed of arbitrarily shaped metals, arrayed vias, and DMOS transistors. We use FEM to extract the parasitic resistance of the source/drain metals since its strong contribution to Ron. In order to handle the large design case and accelerate the extraction process, a domain decomposition with virtual terminal insertion method is introduced, which succeeds in extraction for a set of industrial test cases including those the FEM without domain decomposition failed in. For a layout in which the DMOS cells are regularly placed, a sub-domain reuse procedure is also proposed, which obtained a dramatic speedup for the extraction. Even without the sub-domain reuse, our method still shows advantage in runtime and memory usage according to the simulation results.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.2 pp.542-549
- Publication Date
- 2008/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e91-a.2.542
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
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Bo YANG, Hiroshi MURATA, Shigetoshi NAKATAKE, "A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion" in IEICE TRANSACTIONS on Fundamentals,
vol. E91-A, no. 2, pp. 542-549, February 2008, doi: 10.1093/ietfec/e91-a.2.542.
Abstract: This paper addresses the on-resistance (Ron) extraction of the DMOS based driver in Power IC designs. The proposed method can extract Ron of a driver from its layout data for the arbitrarily shaped metallization patterns. Such a driver is usually composed of arbitrarily shaped metals, arrayed vias, and DMOS transistors. We use FEM to extract the parasitic resistance of the source/drain metals since its strong contribution to Ron. In order to handle the large design case and accelerate the extraction process, a domain decomposition with virtual terminal insertion method is introduced, which succeeds in extraction for a set of industrial test cases including those the FEM without domain decomposition failed in. For a layout in which the DMOS cells are regularly placed, a sub-domain reuse procedure is also proposed, which obtained a dramatic speedup for the extraction. Even without the sub-domain reuse, our method still shows advantage in runtime and memory usage according to the simulation results.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.2.542/_p
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@ARTICLE{e91-a_2_542,
author={Bo YANG, Hiroshi MURATA, Shigetoshi NAKATAKE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion},
year={2008},
volume={E91-A},
number={2},
pages={542-549},
abstract={This paper addresses the on-resistance (Ron) extraction of the DMOS based driver in Power IC designs. The proposed method can extract Ron of a driver from its layout data for the arbitrarily shaped metallization patterns. Such a driver is usually composed of arbitrarily shaped metals, arrayed vias, and DMOS transistors. We use FEM to extract the parasitic resistance of the source/drain metals since its strong contribution to Ron. In order to handle the large design case and accelerate the extraction process, a domain decomposition with virtual terminal insertion method is introduced, which succeeds in extraction for a set of industrial test cases including those the FEM without domain decomposition failed in. For a layout in which the DMOS cells are regularly placed, a sub-domain reuse procedure is also proposed, which obtained a dramatic speedup for the extraction. Even without the sub-domain reuse, our method still shows advantage in runtime and memory usage according to the simulation results.},
keywords={},
doi={10.1093/ietfec/e91-a.2.542},
ISSN={1745-1337},
month={February},}
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TY - JOUR
TI - A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 542
EP - 549
AU - Bo YANG
AU - Hiroshi MURATA
AU - Shigetoshi NAKATAKE
PY - 2008
DO - 10.1093/ietfec/e91-a.2.542
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2008
AB - This paper addresses the on-resistance (Ron) extraction of the DMOS based driver in Power IC designs. The proposed method can extract Ron of a driver from its layout data for the arbitrarily shaped metallization patterns. Such a driver is usually composed of arbitrarily shaped metals, arrayed vias, and DMOS transistors. We use FEM to extract the parasitic resistance of the source/drain metals since its strong contribution to Ron. In order to handle the large design case and accelerate the extraction process, a domain decomposition with virtual terminal insertion method is introduced, which succeeds in extraction for a set of industrial test cases including those the FEM without domain decomposition failed in. For a layout in which the DMOS cells are regularly placed, a sub-domain reuse procedure is also proposed, which obtained a dramatic speedup for the extraction. Even without the sub-domain reuse, our method still shows advantage in runtime and memory usage according to the simulation results.
ER -
English
