In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).

Improving robustness in electrostatic discharge (ESD) protection by inserting drain-side isolated silicon-controlled rectifiers (SCRs) in a high-voltage (HV) p-channel lateral-diffused MOSFET (pLDMOS) device was investigated in this paper. Additionally, the effects of anti-ESD reliability in the HV pLDMOS transistors provided by this technique were evaluated. From the experimental data, it was determined that the holding voltage (Vh) values of the pLDMOS with an embedded npn-arranged SCR and discrete thin-oxide (OD) layout on the cathode side increased as the parasitic SCR OD row number decreased. Moreover, the trigger voltage (Vt1) and the Vh values of the pLDMOS with a parasitic pnp-arranged SCR and discrete OD layout on the drain side fluctuated slightly as the SCR OD-row number decreased. Furthermore, the secondary breakdown current (It2) values (i.e., the equivalent ESD-reliability robustness) of all pLDMOS-SCR npn-arranged types increased (>408.4%) to a higher degree than those of the pure pLDMOS, except for npn-DIS_3 and npn-DIS_2, which had low areas of SCRs. All pLDMOS-SCR pnp-arranged types exhibited an increase of up to 2.2A-2.4A, except for the pnp_DIS_3 and pnp_DIS_2 samples; the pnp_DIS_91 increased by approximately 2000.9% (249.1%), exhibiting a higher increase than that of the reference pLDMOS (i.e., the corresponding pnp-stripe type). The ESD robustness of the pLDMOS-SCR pnp-arranged type and npn-arranged type with a discrete OD layout on the SCR cathode side was greater than that of the corresponding pLDMOS-SCR stripe type and a pure pLDMOS, particularly in the pLDMOS-SCR pnp-arranged type.

In this paper, we aim to investigate the potential usefulness of machine learning in image quality assessment (IQA). Most previous studies have focused on designing effective image quality metrics (IQMs), and significant advances have been made in the development of IQMs over the last decade. Here, our goal is to improve prediction outcomes of “any” given image quality metric. We call this the “IQM's Outcome Improvement” problem, in order to distinguish the proposed approach from the existing IQA approaches. We propose a method that focuses on the underlying IQM and improves its prediction results by using machine learning techniques. Extensive experiments have been conducted on three different publicly available image databases. Particularly, through both 1) in-database and 2) cross-database validations, the generality and technological feasibility (in real-world applications) of our machine-learning-based algorithm have been evaluated. Our results demonstrate that the proposed framework improves prediction outcomes of various existing commonly used IQMs (e.g., MSE, PSNR, SSIM-based IQMs, etc.) in terms of not only prediction accuracy, but also prediction monotonicity.

This paper discusses Mixed Signal LSI technology with embedded power transistors. Trends in Mixed Signal LSI technology are explained at first. Mixed signal LSI technology has proceeded with the help of fine fabrication technology and SOI technology. The BEOL transistor is a new development, which uses InGaZnO (IGZO) as its TFT channel material. The BEOL transistor is one future device which enables 3D IC and chip shrinking technology.

Two voltage controlled current source (VCCS) models of double-channel p-type lateral extended drain MOS (DPLEDMOS) are firstly proposed to analyze the energy recovery circuit (ERC) efficiency of PDP data driver IC. In terms of the mathematical function between ID and VDS, the VCCS models are created. The presented models can be embedded in system software Saber to simulate the ERC waveform of data driver IC. A test board and a PDP system are used to verify the accuracy of the VCCS models. The experimental measurements agree with the simulation results very well and the maximum model error is 3.89%. Simulation results also show that the ERC efficiency of PDP data driver IC is influenced by three factors: the value of charge time TERC, the drain current ID, and the capacitance of CL. In an actual PDP system, TERC is restricted and CL is changeless. The ERC efficiency of PDP data driver IC can be improved significantly by using DPLEDMOS which has higher ID capacity. The proposed VCCS models of DPLEDMOS can be used to predict the ERC efficiency accurately.

The trench-gate type high-voltage (HV) MOSFET is one of the variants of HV-MOSFET, typically with its utility segments lying on a larger power consumption domain, compared to planar HV-MOSFETs. In this work, the HiSIM_HV compact model, originally intended for planar LDMOSFETs, was adequately extended to accommodate trench-gate type HV-MOSFETs. The model formulation focuses on a closed-form description of the current path in the highly resistive drift region, specific to the trench-gate HV-MOSFETs. It is verified that the developed compact expression can capture the conductivity in the drift region, which varies with voltage bias and device technology such as trench width. The notable enhancement of current drivability can be accounted for by the electrostatic control exerted by the trench gate within the framework of this model.

A novel NMOS Electrostatic Discharge (ESD) clamp circuit is proposed for a 0.35 µm Bipolar-CMOS-DMOS (BCD) process. The proposed ESD clamp has a non-snapback characteristic because of gate-coupled effect. This proposed ESD clamp circuit is developed without additional components made possible by replacing a capacitor with an isolated parasitic capacitor. The result of the proposed ESD clamp circuit is measured by 100 ns Transmission Line Pulse (TLP) system. From the measurement, it was observed that the proposed ESD clamp has approximately 40% lower triggering voltage compared to the conventional gate-grounded NMOS ESD clamp. This is achieved without degradation of the other ESD design key parameter. The proposed ESD clamp also has high robustness characteristics compared to the conventional RC-triggered NMOS ESD clamp circuit.

We have developed a macro model, which allows us to describe precise LDMOS DC/AC characteristics. Characterization of anomalous gate input capacitance is the key issue in the LDMOS model development. We have newly employed a T-type distributed RC scheme for gate overlapped LDMOS drift region. The bias dependent resistance and capacitance are modeled independently in Verilog-A as R-model and PMOS-capacitance. The dividing factor of the distributed R is introduced to reflect the shield effect of the gate overlap capacitance. Comparison between the new model and measurement results has proven that the developed macro model reproduces accurately not only the gate input capacitance, but also DC characteristics.

A scalable DC model of lateral double diffused MOSFETs (LDMOSFETs) is presented in this paper. This model is based on physical analysis considering device geometry, carrier distributions, mobility degradation effect, and the effect of impact ionization. In this model, we divide the LDMOSFET into two regions to obtain the physical conduction model: one is channel region and the other is drift region. The channel region model is based on the BSIM3v3 model and the drift region employs voltage dependent resistance model considering the length of depleted region in the drift region. The modeling results are compared with measured I-V characteristics and the results show good agreements with the maximum error of 10% compared to the measured results of devices.

This paper addresses the on-resistance (Ron) extraction of the DMOS based driver in Power IC designs. The proposed method can extract Ron of a driver from its layout data for the arbitrarily shaped metallization patterns. Such a driver is usually composed of arbitrarily shaped metals, arrayed vias, and DMOS transistors. We use FEM to extract the parasitic resistance of the source/drain metals since its strong contribution to Ron. In order to handle the large design case and accelerate the extraction process, a domain decomposition with virtual terminal insertion method is introduced, which succeeds in extraction for a set of industrial test cases including those the FEM without domain decomposition failed in. For a layout in which the DMOS cells are regularly placed, a sub-domain reuse procedure is also proposed, which obtained a dramatic speedup for the extraction. Even without the sub-domain reuse, our method still shows advantage in runtime and memory usage according to the simulation results.

Vertical Power MOSFETs are widely designed by deep well structures for breakdown requirement. In this study, we proposed, simulated, and analyzed a "shallow dual well" structure Power MOSFET, which utilize an n-well to cover the conventional p-well. The cell pitch can be reduced and results in an increased cell density. The reduced cell pitch and increased cell density improves the gate charge and on resistance performances about 66.5% and 15.8% without sacrificing the device breakdown owing to a shallow junction design. In addition, with the dual well structure design, the breakdown point will occur at the center of the well. Therefore, the capability of avalanche energy can be improved about 1.9 times than the tradition well structure.

In this paper, a preprocessing approach to improving the quality of the music on a mobile phone using Enhanced variable rate codec (EVRC) is presented. Our approach works well on music signals considerably reducing the number of time-clipped frames.

This paper proposes an LDMOSFET (Lateral Double-diffused MOSFET) that has the robustness against the hardest ESD (Electrostatic Discharge) requirement for automobile ECUs (Electronic Control Units) of discharging 25 kV 150 pF through 150 ohm 1 µH without external protecting circuits. The basic idea to achieve this is to add a novel discharge circuit to an LDMOSFET, which turns on when Human Body Model (HBM) type ESD is applied, and to consume the discharge energy in SOA (Safe Operating Area) in the LDMOSFET, avoiding localized current crowding of a parasitic bipolar transistor which causes the conventional ESD device failure. First, dynamics of current crowding when a grounded gate LDMOSFET is exposed to ESD stress is described by means of a circuit level SPICE simulation on a parallel distributed device model. Then a novel ESD turn-on LDMOSFET with a discharge MOSFET is proposed, which has ESD robustness of 25 kV. Finally the ESD measurements of the new device are shown to be in good accordance with estimation and to satisfy the target.

EL (Electroluminescent) displays have been applied to automobiles, as their images are very clear and bright. High voltage, high integration and low power dissipation ICs are needed to drive these devices. To meet this, high voltage CMOS ICs using SOI (Silicon On Insulator) substrates are chosen as the driving devices. In this paper, an isolation structure between the output CMOS devices, of high density and high voltage is proposed. Conventional trench dielectric isolation shows degradation of a break down voltage with short distance from trench to source. In this work, the authors make clear the electric field distribution near the isolation, and offer a novel structure of "Field-plate Trench Isolation," which enables to relax the electric field on the silicon surface by shifting a part of electric field into surface oxide. Finally, operation of high voltage and high density, a 200-volt and 32-channel, EL display driver for automotive display panel is confirmed.

A complex modular process flow was developed for PRISM technology to permit increased system integration. In order to combine the required functions--submicron CMOS Logic, Nonvolatile Memories, Precision Linear, and Power Drivers--on a monolithic silicon chip, a highly structured, systematic approach to process synthesis was developed. TCAD tools were used extensively for process design and verification. The 60 V LDMOS power transistor and the Flash memory cell built in the technology will be described to illustrate the process synthesis methodology.