Layout Dependent Matching Analysis of CMOS Circuits
Summary :
Layout has strong influence on matching properties of a circuit. Current matching models, which characterize both local random non-uniformities and global systematic non-uniformities stochastically, are not adequate for the matching analysis taking the effect of layout realization into account. In order to consider topological information of layout into matching analysis, we propose a matching model which treats the random and systematic components separately. Also, we characterize the micro-loading effect, which modulates fabricated line-width according to the local density of layout patterns, into matching analysis. With these two techniques, we can perform matching analysis of CMOS circuits taking layout information into account.
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- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.2 pp.348-355
- Publication Date
- 1999/02/25
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- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
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Kenichi OKADA, Hidetoshi ONODERA, Keikichi TAMARU, "Layout Dependent Matching Analysis of CMOS Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 2, pp. 348-355, February 1999, doi: .
Abstract: Layout has strong influence on matching properties of a circuit. Current matching models, which characterize both local random non-uniformities and global systematic non-uniformities stochastically, are not adequate for the matching analysis taking the effect of layout realization into account. In order to consider topological information of layout into matching analysis, we propose a matching model which treats the random and systematic components separately. Also, we characterize the micro-loading effect, which modulates fabricated line-width according to the local density of layout patterns, into matching analysis. With these two techniques, we can perform matching analysis of CMOS circuits taking layout information into account.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_2_348/_p
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@ARTICLE{e82-a_2_348,
author={Kenichi OKADA, Hidetoshi ONODERA, Keikichi TAMARU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Layout Dependent Matching Analysis of CMOS Circuits},
year={1999},
volume={E82-A},
number={2},
pages={348-355},
abstract={Layout has strong influence on matching properties of a circuit. Current matching models, which characterize both local random non-uniformities and global systematic non-uniformities stochastically, are not adequate for the matching analysis taking the effect of layout realization into account. In order to consider topological information of layout into matching analysis, we propose a matching model which treats the random and systematic components separately. Also, we characterize the micro-loading effect, which modulates fabricated line-width according to the local density of layout patterns, into matching analysis. With these two techniques, we can perform matching analysis of CMOS circuits taking layout information into account.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - Layout Dependent Matching Analysis of CMOS Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 348
EP - 355
AU - Kenichi OKADA
AU - Hidetoshi ONODERA
AU - Keikichi TAMARU
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 1999
AB - Layout has strong influence on matching properties of a circuit. Current matching models, which characterize both local random non-uniformities and global systematic non-uniformities stochastically, are not adequate for the matching analysis taking the effect of layout realization into account. In order to consider topological information of layout into matching analysis, we propose a matching model which treats the random and systematic components separately. Also, we characterize the micro-loading effect, which modulates fabricated line-width according to the local density of layout patterns, into matching analysis. With these two techniques, we can perform matching analysis of CMOS circuits taking layout information into account.
ER -
English
