IEICE TRANSACTIONS on Fundamentals
Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process
Summary :
This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/ 14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.8 pp.1359-1365
- Publication Date
- 2012/08/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.1359
- Type of Manuscript
- PAPER
- Category
- Reliability, Maintainability and Safety Analysis
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Shusuke YOSHIMOTO, Takuro AMASHITA, Shunsuke OKUMURA, Koji NII, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI, "Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 8, pp. 1359-1365, August 2012, doi: 10.1587/transfun.E95.A.1359.
Abstract: This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/ 14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.1359/_p
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@ARTICLE{e95-a_8_1359,
author={Shusuke YOSHIMOTO, Takuro AMASHITA, Shunsuke OKUMURA, Koji NII, Masahiko YOSHIMOTO, Hiroshi KAWAGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process},
year={2012},
volume={E95-A},
number={8},
pages={1359-1365},
abstract={This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/ 14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.},
keywords={},
doi={10.1587/transfun.E95.A.1359},
ISSN={1745-1337},
month={August},}
Copy
TY - JOUR
TI - Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1359
EP - 1365
AU - Shusuke YOSHIMOTO
AU - Takuro AMASHITA
AU - Shunsuke OKUMURA
AU - Koji NII
AU - Masahiko YOSHIMOTO
AU - Hiroshi KAWAGUCHI
PY - 2012
DO - 10.1587/transfun.E95.A.1359
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 8
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - August 2012
AB - This paper presents measurement results of bit error rate (BER) and soft error rate (SER) improvement on 150-nm FD-SOI 7T/14T (7-transistor/ 14-transistor) SRAM test chips. The reliability of the 7T/14T SRAM can be dynamically changed by a control signal depending on an operating condition and application. The 14T dependable mode allocates one bit in a 14T cell and improves the BER in a read operation and SER in a retention state, simultaneously. We investigate its error rate mitigating mechanisms using Synopsys TCAD simulator. In our measurements, the minimum operating voltage was improved by 100 mV, the alpha-induced SER was suppressed by 80.0%, and the neutron-induced SER was decreased by 34.4% in the 14T dependable mode over the 7T normal mode.
ER -
English
