IEICE TRANSACTIONS on Information
A Low Power Deterministic Test Using Scan Chain Disable Technique
Summary :
This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In this scheme the flip-flops are grouped into N scan chains. At any time, only one scan chain is active during scan test. Therefore, both average power and peak power are reduced compared with conventional full scan test methodology. This paper also proposes a tabu search-based approach to minimize test application time. In this approach we handle the information during deterministic test efficiently. Experimental results demonstrate that this approach drastically reduces both average power and peak power dissipation at a little longer test application time on various benchmark circuits.
- Publication
- IEICE TRANSACTIONS on Information Vol.E89-D No.6 pp.1931-1939
- Publication Date
- 2006/06/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e89-d.6.1931
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Keyword
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Zhiqiang YOU, Tsuyoshi IWAGAKI, Michiko INOUE, Hideo FUJIWARA, "A Low Power Deterministic Test Using Scan Chain Disable Technique" in IEICE TRANSACTIONS on Information,
vol. E89-D, no. 6, pp. 1931-1939, June 2006, doi: 10.1093/ietisy/e89-d.6.1931.
Abstract: This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In this scheme the flip-flops are grouped into N scan chains. At any time, only one scan chain is active during scan test. Therefore, both average power and peak power are reduced compared with conventional full scan test methodology. This paper also proposes a tabu search-based approach to minimize test application time. In this approach we handle the information during deterministic test efficiently. Experimental results demonstrate that this approach drastically reduces both average power and peak power dissipation at a little longer test application time on various benchmark circuits.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e89-d.6.1931/_p
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@ARTICLE{e89-d_6_1931,
author={Zhiqiang YOU, Tsuyoshi IWAGAKI, Michiko INOUE, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={A Low Power Deterministic Test Using Scan Chain Disable Technique},
year={2006},
volume={E89-D},
number={6},
pages={1931-1939},
abstract={This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In this scheme the flip-flops are grouped into N scan chains. At any time, only one scan chain is active during scan test. Therefore, both average power and peak power are reduced compared with conventional full scan test methodology. This paper also proposes a tabu search-based approach to minimize test application time. In this approach we handle the information during deterministic test efficiently. Experimental results demonstrate that this approach drastically reduces both average power and peak power dissipation at a little longer test application time on various benchmark circuits.},
keywords={},
doi={10.1093/ietisy/e89-d.6.1931},
ISSN={1745-1361},
month={June},}
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TY - JOUR
TI - A Low Power Deterministic Test Using Scan Chain Disable Technique
T2 - IEICE TRANSACTIONS on Information
SP - 1931
EP - 1939
AU - Zhiqiang YOU
AU - Tsuyoshi IWAGAKI
AU - Michiko INOUE
AU - Hideo FUJIWARA
PY - 2006
DO - 10.1093/ietisy/e89-d.6.1931
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E89-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2006
AB - This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In this scheme the flip-flops are grouped into N scan chains. At any time, only one scan chain is active during scan test. Therefore, both average power and peak power are reduced compared with conventional full scan test methodology. This paper also proposes a tabu search-based approach to minimize test application time. In this approach we handle the information during deterministic test efficiently. Experimental results demonstrate that this approach drastically reduces both average power and peak power dissipation at a little longer test application time on various benchmark circuits.
ER -
English
