This paper proposes a low power scan test scheme and formulates a problem based on this scheme. In this scheme the flip-flops are grouped into N scan chains. At any time, only one scan chain is active during scan test. Therefore, both average power and peak power are reduced compared with conventional full scan test methodology. This paper also proposes a tabu search-based approach to minimize test application time. In this approach we handle the information during deterministic test efficiently. Experimental results demonstrate that this approach drastically reduces both average power and peak power dissipation at a little longer test application time on various benchmark circuits.

In delay fault BIST (Built-In-Self-Test), an adjacency test pattern generation scheme effectively generates robust test patterns. The traditional adjacency test pattern generation schemes use LFSR to generate first patterns, and thus they cannot generate test patterns for circuits with more than 30 inputs with high fault coverage in a practical amount of time. This paper proposes a deterministic delay fault BIST method using adjacency test pattern generation. The proposed scheme uses first patterns generated by a deterministic algorithm based on the analysis of independent partial circuits on the circuit under test. Experiments show that test patterns generated by the proposed method have both high fault coverage and short test length, resulting in a short test time.