High Speed DSA 4 Kbit Static RAM

Mitsutaka MORIMOTO; Kazukiyo TAKAHASHI; Hiroki MUTA

High Speed DSA 4 Kbit Static RAM

Mitsutaka MORIMOTO, Kazukiyo TAKAHASHI, Hiroki MUTA

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A high speed, 4 K word by one bit static Random Access Memory (RAM) has been developed, using Diffusion Self-Aligned (DSA) MOS technology. High speed and low power operation was achieved by combining the following refined devices and new circuit technology; high gain DSA MOS FETs as drivers, Reverse DSA (RDSA) MOS FETs with low threshold voltage (V_TAR0 V) as power reduction switches, full wave rectifier substrate bias generator and dual X-decoder circuits. The present RAM operates on a single 51 V external power supply. Its typical performances are; 28 ns chip enable access time (C_L33 pF), 300 mW active power dissipation and 50 mW stand-by power dissipation.

Publication: IEICE TRANSACTIONS on transactions Vol.E63-E No.7 pp.520-525

Publication Date: 1980/07/25

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Type of Manuscript: PAPER

Category: Integrated Circuits

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Mitsutaka MORIMOTO
Kazukiyo TAKAHASHI
Hiroki MUTA

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Mitsutaka MORIMOTO, Kazukiyo TAKAHASHI, Hiroki MUTA, "High Speed DSA 4 Kbit Static RAM" in IEICE TRANSACTIONS on transactions, vol. E63-E, no. 7, pp. 520-525, July 1980, doi: .
Abstract: A high speed, 4 K word by one bit static Random Access Memory (RAM) has been developed, using Diffusion Self-Aligned (DSA) MOS technology. High speed and low power operation was achieved by combining the following refined devices and new circuit technology; high gain DSA MOS FETs as drivers, Reverse DSA (RDSA) MOS FETs with low threshold voltage (V_TAR0 V) as power reduction switches, full wave rectifier substrate bias generator and dual X-decoder circuits. The present RAM operates on a single 51 V external power supply. Its typical performances are; 28 ns chip enable access time (C_L33 pF), 300 mW active power dissipation and 50 mW stand-by power dissipation.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e63-e_7_520/_p

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@ARTICLE{e63-e_7_520,
author={Mitsutaka MORIMOTO, Kazukiyo TAKAHASHI, Hiroki MUTA, },
journal={IEICE TRANSACTIONS on transactions},
title={High Speed DSA 4 Kbit Static RAM},
year={1980},
volume={E63-E},
number={7},
pages={520-525},
abstract={A high speed, 4 K word by one bit static Random Access Memory (RAM) has been developed, using Diffusion Self-Aligned (DSA) MOS technology. High speed and low power operation was achieved by combining the following refined devices and new circuit technology; high gain DSA MOS FETs as drivers, Reverse DSA (RDSA) MOS FETs with low threshold voltage (V_TAR0 V) as power reduction switches, full wave rectifier substrate bias generator and dual X-decoder circuits. The present RAM operates on a single 51 V external power supply. Its typical performances are; 28 ns chip enable access time (C_L33 pF), 300 mW active power dissipation and 50 mW stand-by power dissipation.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - High Speed DSA 4 Kbit Static RAM
T2 - IEICE TRANSACTIONS on transactions
SP - 520
EP - 525
AU - Mitsutaka MORIMOTO
AU - Kazukiyo TAKAHASHI
AU - Hiroki MUTA
PY - 1980
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E63-E
IS - 7
JA - IEICE TRANSACTIONS on transactions
Y1 - July 1980
AB - A high speed, 4 K word by one bit static Random Access Memory (RAM) has been developed, using Diffusion Self-Aligned (DSA) MOS technology. High speed and low power operation was achieved by combining the following refined devices and new circuit technology; high gain DSA MOS FETs as drivers, Reverse DSA (RDSA) MOS FETs with low threshold voltage (V_TAR0 V) as power reduction switches, full wave rectifier substrate bias generator and dual X-decoder circuits. The present RAM operates on a single 51 V external power supply. Its typical performances are; 28 ns chip enable access time (C_L33 pF), 300 mW active power dissipation and 50 mW stand-by power dissipation.
ER -