This paper describes a speed-oriented ultralow-voltage and low-power SOI circuit technique based on a differential enhancement- and depletion-mode (ED)-MOS circuit. Combining an ED-MOS circuit block for critical paths and a multi-Vth CMOS circuit block for noncritical paths, that is, the so-called differential ED-CMOS/SOI circuit, makes it possible to achieve low-power and ultrahigh-speed operation of over 1 GHz at a supply voltage of less than 0.5 V. As two applications of the differential ED-CMOS/SOI circuit, a multi-stage frequency divider that uses the ED-MOS circuit in a first-stage frequency divider and a pipelined adder with a CMOS pipeline register are described in detail. To verify the effectiveness of the ED-CMOS/SOI circuit scheme, we fabricated a 1/8 frequency divider and a 32-bit binary look-ahead carry (BLC) adder using the 0.25-µm MTCMOS/SOI process. The frequency divider operates down to 0.3 V with a maximum operating frequency of 3.6 GHz while suppressing power dissipation to 0.3 mW. The 32-bit adder operates at a frequency of 1 GHz at 0.5 V.

This paper describes logic and analog test schemes that improve the testability of a pixel-parallel fingerprint identification circuit. The pixel contains a processing circuit and a capacitive fingerprint sensor circuit. For the logic test, we propose a test method using a pseudo scan circuit to check the processing circuits of all pixels simultaneously. In the analog test, the sensor circuit employs dummy capacitance to mimic the state of a finger touching the chip. This enables an evaluation of the sensitivity of all sensor circuits on logical LSI tester without touching the chip with a finger. To check the effectiveness of the schemes, we applied them to a pixel array in a fingerprint identification LSI. The pseudo scan circuit achieved a 100% failure-detection rate for the processing circuit. The analog test determines that the sensitivities of the sensor circuit in all pixels are in the proper range. The results of the tests confirmed that the proposed schemes can completely detect defects in the circuits. Thus, the schemes will pave the way to logic and analog tests of chips integrating highly functional devices stacked on a LSI.

This paper presents fingerprint image enhancement and rotation schemes that improve the identification accuracy with the pixel-parallel processing of pixels. In the schemes, the range of the fingerprint sensor is adjusted to the finger state, the captured image is retouched to obtain the suitable image for identification, and the image is rotated to the correct angle on the pixel array. Sensor and pixel circuits that provide these operations were devised and a test chip was fabricated using 0.25-µm CMOS and the sensor process. It was confirmed in 150,000 identification tests that the schemes reduce the false rejection rate to 6.17% from 30.59%, when the false acceptance rate is 0.1%.

This paper describes an adaptive fingerprint-sensing scheme for a user authentication system with a fingerprint sensor LSI to obtain high-quality fingerprint images suitable for identification. The scheme is based on novel evaluation indexes of fingerprint-image quality and adjustable analog-to-digital (A/D) conversion. The scheme adjusts dynamically an A/D conversion range of the fingerprint sensor LSI while evaluating the image quality during real-time fingerprint-sensing operation. The evaluation indexes pertain to the contrast and the ridgelines of a fingerprint image. The A/D conversion range is adjusted by changing quantization resolution and offset. We developed a fingerprint sensor LSI and a user authentication system to evaluate the adaptive fingerprint-sensing scheme. The scheme obtained a fingerprint image suitable for identification and the system achieved an accurate identification rate with 0.36% of the false rejection rate (FRR) at 0.075% of the false acceptance rate (FAR). This confirms that the scheme is very effective in achieving accurate identification.

This paper investigates the application of inter-cell interference coordination (ICIC) in heterogeneous networks for the LTE-Advanced downlink where picocells are overlaid onto macrocells. In LTE-Advanced, in order to perform ICIC, almost blank subframes (ABSs) are employed, where only the cell-specific reference signal (CRS) is transmitted to protect the subframes in the picocells from severe interference from the macrocells. Furthermore, multicast/broadcast over single-frequency network (MBSFN) subframes are employed to reduce the interference of the CRS on the data channel, although the control channel still suffers from interference from the CRS. When the cell range expansion (CRE), which offload the UEs from macrocells to picocells, is used to improve the system performance, the influence from the CRS increases. In order to assess the influence, the required CRE bias to improve the data channel is investigated based on a system-level simulation under various conditions such as the number of picocells, the protected subframe ratio, and the user distribution. The simulation results show that the cell-edge user throughput is improved with the CRE bias of more than 8 dB, employing ABSs. Furthermore, simulation results show that one dominant source of interference is observed for the sets of user equipment (UEs) connected to the picocells via CRE with such a bias value. Based on observation, the influence that the CRS has on the control channel, i.e., physical control format indicator channel (PCFICH), and physical downlink control channel (PDCCH) is investigated based on a link-level simulation combined with a system-level simulation. The simulation results show that protecting the PCFICH is very important compared to protecting the PDCCH, since the block error rate (BLER) performance of the PCFICH becomes worse than the required BLER of 10-3 to support various conditions, although the BLER performance of the PDCCH can exceed the required BLER of 10-2 by spanning the PDCCH over three OFDM symbols.

This paper describes the effect of lowering the supply voltage and threshold voltages on the energy reduction of an ultralow-voltage multi-threshold CMOS/SIMOX (MTCMOS/SIMOX) circuit. The energy dissipation is evaluated using a graph with equispeed and equienergy lines on a supply voltage and a threshold voltage plane. In order to draw equispeed and equienergy lines for ultralow-voltage circuits, we propose a modified energy-evaluation model taking into account a input-waveform transition-time of the circuits. The validity of the proposed energy-evaluation model is confirmed by the evaluation of a gate-chain TEG and a 16-bit CLA adder fabricated with 0.25-µm MTCMOS/SIMOX technology. Using the modified model, the energy-reduction effect in lowering the supply voltage is evaluated for a single-Vth fully-depleted CMOS/SOI circuit, a dual-Vth CMOS circuit consisting of fully-depleted low- and medium-Vth MOSFETs, and a triple-Vth MTCMOS/SIMOX circuit. The evaluation reveals that lowering the supply voltage of the MTCMOS/SIMOX circuit to 0.5 V is advantageous for the energy reduction at a constant operating speed.

A new threshold circuit technique is proposed for a vibration sensing circuit that operates at a nanowatt power level. The sensing circuits that use sample-and-hold require a clock signal, and they consume power to generate a signal. In the use of a Schmitt trigger circuit that does not use a clock signal, a sink current flows when thresholding the analog signal output. The requirements for millimeter-sized wireless sensor nodes are an average power on the order of a nanowatt and a signal transition time of less than 1 ms. To meet these requirements, our circuit limits the sink current with a nanoampere-level current source. The chattering caused by current limiting is suppressed by feeding back the change in output voltage to the limiting current. The increase in the signal transition time that is caused by current limiting is reduced by accelerating the discharge of the load capacitance. For a test chip fabricated in the 0.35-µm CMOS process, the proposed threshold circuits operate without chattering and the average powers are 0.7-3 nW. The signal transition times are estimated in a circuit simulation to be 65-97 µs. The proposed circuit has 1/150th the power-delay product with no time interval of the sensing operation under the condition that the time interval is 1s. These results indicate that, the proposed threshold circuits are suitable for vibration sensing in millimeter-sized wireless sensor nodes.

In Long-Term Evolution (LTE)-Advanced, heterogeneous networks where femtocells and picocells are overlaid onto macrocells are extensively discussed in addition to traditional well-planned macrocell deployment to improve further the system throughput. In heterogeneous network deployment, combined usage of inter-cell interference coordination (ICIC) and cell range expansion (CRE) is very effective in improving the system and cell-edge throughput. In this combined usage, the fraction of the sets of user equipment (UEs) connected to the picocells, which are controlled through CRE, and that connected to macrocells affect the gain from the ICIC. Therefore, this paper evaluates the throughput performance of different offset values for CRE and different amounts of protected resources for ICIC in picocell deployments in LTE-Advanced downlink. Simulation results (2–10 picocells and 30 UEs are located within 1 macrocell) assuming a full buffer traffic model show that when the CRE offset value is set between 8 to 20 dB, almost the same user throughput performance is obtained by allocating the appropriate resources to protect UEs that connect to the picocells. Furthermore, the appropriate resource ratio is derived based on the fraction of UEs connected to the picocells through CRE, the fraction of UEs connected to the macrocell, and the number of picocells under the simulation conditions.

The design and performance of a sub-nanoampere two-stage power management circuit that uses off-chip capacitors for energy accumulation are presented. Focusing on the leakage current and the transition time of the power switch transistor, we estimated the minimum current for accumulating. On the basis of the results, we devised a two-stage power management architecture for sub-nanoampere operation. The simulated and experimental results for the power management circuit describe the accumulating operation with a 1-nA current source.

A self-powered flyback pulse resonant circuit (FPRC) is proposed to extract energy from piezoelectric (PEG) and thermoelectric generators (TEG) simultaneously. The FPRC is able to cold start with the PEG voltage regardless of the TEG voltage, which means the TEG energy is extracted without additional cost. The measurements show that the FPRC can output 102 µW power under the input PEG and TEG voltages of 2.5 V and 0.5 V, respectively. The extracted power is increased by 57.6% compared to the case without TEGs. Additionally, the power improvement with respect to an ideal full-wave bridge rectifier is 2.71× with an efficiency of 53.9%.