A monolithic linear power amplifier IC operating with a single low 2.7-V supply has been developed for 1.9-GHz digital mobile communication systems, such as the Japanese personal handy phone system (PHS). Refractory WNx/W self-aligned gate GaAs power MESFETs have been successfully developed for L-band power amplification, and this power amplifier operates with high efficiency and low distortion at a low voltage of 2.7 V, without any additional negative voltage supply, by virtue of small drain knee voltage, high transconductance and sufficient breakdown voltage of the power MESFET. An output power of 23.0 dBm and a high power-added efficiency of 30.8% were attained for 1.9-GHz π/4-shifted QPSK (quadrature phase shift keying) modulated input when adjacent channel leakage power level was less than -60 dBc at 600 kHz apart from 1.9 GHz.

A GaAs SPDT switch IC operating at a low power supply voltage of 2.7 V has been developed for use in 1.9 GHz band personal handy phone system (PHS). In combination with MESFETs with low on-resistance and high breakdown voltage, the switch IC adopts parallel-LC resonant circuits and utilizes both stacked FETs and an additional shunt capacitor at the receiver side in order to realize low insertion loss, high isolation and low distortion characteristics. An insertion loss of 0.55 dB and an isolation of 35.8 dB were obtained at 1.9 GHz. The IC also achieved an output power of 25.0 dBm at 1 dB gain compression point, a second order distortion of -54.3 dBc and an adjacent channel leakage power of -66 dBc at 600 kHz apart from 1.9 GHz at 19 dBm output power.

Layout-aware compact models proposed so far have been generally verified only for simple test patterns. However, real designs use much more complicated layout patterns. Therefore, models must be verified for such patterns to establish their practicality. This paper proposes a methodology and test patterns for exhaustively and systematically validating layout-aware compact models for general layout patterns for the first time. The methodology and test patterns are concretely shown through validation of a shallow trench isolation (STI) stress compact model proposed in [1]. First, the model parameters for a 55-nm CMOS technology are extracted, and then the model is verified and established to be accurate for the basic patterns used for parameter extraction. Next, fundamental ideas of model operation for general layout patterns are verified using various verification patterns. These tests revealed that the model is relatively weak in some cases not included in the basic patterns. Finally, the errors for these cases are eliminated by enhancing the algorithm. Consequently, the model is confirmed to have high generality. This methodology will be effective for validating other layout-aware compact models for general layout patterns.

This paper proposes an off-line text-independent writer identification method applicable to Japanese and Korean sentences. It is assumed that the writer of a writing in question exists in a certain group of people and that reference writings written by each person in the group can be used for identification. In the proposed method, relative frequencies of some model patterns are counted on the binary pattern of each writing and are used as the feature to measure the distance between two writings. Based on a modified Mahalanobis' distance for this feature, the person whose reference writing is nearest to the writing in question is judged as the writer. The effectiveness of the proposed method is examined through an experiment using Japanese and Korean writings. Error rates in the experiment were different depending on conditions such as volume of reference writings, dimension of adopted features, and number of people to be identified. In some cases, error rates as low as 0% were observed. Error rates tend to be lower in Korean writings probably because Hangul is composed of a smaller number of letters compared to Kanji and Hiragana in Japanese writing.

A GaAs linear power amplifier operating with a single 3-V supply has been developed for 5.8-GHz ISM band applications. Two kinds of refractory WNx/W self-aligned gate MESFETs, a P-pocket MESFET and an asymmetric MESFET with a buried p-layer (BP- MESFET ) have been compared in terms of DC characteristics, small signal characteristics and power performances at 5.8 GHz. To obtain both high gain and high efficiency in the case of single 3-V supply operation at 5.8 GHz, we used a highly efficient and linear P-pocket MESFET for the output-stage power FET and a high-gain asymmetric MESFET with a buried p-layer (BP- MESFET ) for the driver-stage FET. The bias condition for 1-mm output-stage P-pocket MESFET was set near class-AB, so as to obtain sufficient output power with high PAE. The two-stage power amplifier MMIC module which can include all matching and biasing circuits, has been designed and fabricated. The amplifier exhibits a high power gain of 17.9 dB and a high power-added efficiency of 25.7% with a sufficient output power of 18.7 dBm at the 1-dB compression point. This self-aligned gate GaAs MESFET technology is promising for near-future 5.8-GHz applications, because of such good power performance and good mass-producibility.

We report on 1.9-GHz performance of the Buried-Channel self-aligned WN/W-gate GaAs MESFET (BC-MESFET) for use in digital mobile telephone handsets with low power consumption. The BC-MESFET incorporates undoped i-GaAs epitaxial-grown surface layer on the ion-implanted channel. Both the power and noise performance of the BC-MESFET are superior to the conventional MESFET. The 0.6-µm gate power BC-MESFET exhibits a high power-added efficiency of 57% at 1-dB gain compression, which leads to low power dissipation of the handset. This power performance is attributed to high breakdown voltage which the undoped i-GaAs surface layer has brought about. The BC-MESFET has also shown a minimum noise figure of below 0.4 dB. Taking the IC-oriented fabrication process of the BC-MESFET into consideration, these FET performances demonstrate that the BC-MESFET is suitable for the single-chip MMIC that integrates RF front-end blocks for the 1.9-GHz small-size mobile telephone handset with long battery lifetime.

An automatic zip code recognition system for Japanese mail is proposed in this paper. It is assumed that a zip code is composed of three numerals and requited to be written in a specified frame. In actual images, however, the three numerals sometimes extend outside the specified frame and are not clearly separated. Considering this situation, the authors devised a system with two stages, the segmentation stage and the recognition stage. The segmentation stage consists of five steps: setting and adjusting of initial areas for numeral images (figures), calculation of the center of gravity of each figure, search for the horizontal and vertical boundaries of each figure, determination of the final area for each figure, and normalization of the figure in each final area. In the recognition stage, the Localized Arc Pattern Method (Arc method) proposed by Yoshimura et al. (1991) is implemented hierarchically; that is, a simple Arc method is applied first to each figure and a more complex one is applied subsequently unless the figure is identified in the first step. In the recognition process, every figure is judged as a numeral or otherwise rejected. The proposed system was applied to a database provided by the Institute for Post and Telecommunications Policy (IPTP). The segmentation algorithm yielded an adequate result. The recognition algorithm yielded scores as high as 90.6% in correct recognition rate and 0.7% in error rate. The best score of the precision index (P-index) specified by the IPTP was as low as 15.7 for the above mentioned IPTP database, while the score for another IPTP database was 16.9.

There are two purposes in this paper. The one is to compare experimentally the two types of methods of writer identification, structure analysis and pattern matching, and the other is to examine the dependency of identifiability on letters. The material was provided by seven persons who handwrote a sentence of twenty-six letters twenty-five times repeatedly. About a half of the material was used as a sample for learning and the rest was for test. Templates representing persons were constructed from the sample for learning through each of five methods, three of structure analysis S1, S2, S3 and the other two of pattern matching P1, P2. For each character in the sample for test, the distances from it to the templates were evaluated and the person who was the nearest was judged as the writer. Experimentally the average correct identification rate for P1, which is better than P2, was about 85%, while that for S2, which is better than S1 and S3, was about 80%. As far as the methods of structure analysis proposed by us are concerned, they are inferior to the methods of pattern matching. As for sentences, all of the writers were correctly identified. The correct identification rates for HIRAGANA letters are in general greater than those for KATAKANA, which seems to imply that complicated letters transmit us more information about writers than simple letters do.