This paper presents a reconfigurable multi-band class E power amplifier designed in CMOS technology. The proposed class E power amplifier operates efficiently over sparsely separated frequency bands by switching the capacitance of the load network. Simulation results showed a stable and high power added efficiency of 60% with 18.5 dB gain, and 83% with 14.5 dB gain for 2.4 GHz and 5 GHz WLAN applications, respectively.

This paper presents a fast and systematic architecture exploration method that realizes an efficient IEEE 802.11e based hardware/software co-design Medium Access Control (MAC) system architecture, which can achieve near theoretical MAC throughput for burst data transmission while complying with strict channel access time requirements. Our design approach uses SystemC based Transaction Level Modeling (TLM) framework to integrate reconfigurable general purpose computing and communication resources into the application model for rapid evaluation of core parameters, system performance, and application specific optimizations. As a result, a MAC system architecture that achieves a simulated MAC throughput of more than 100 Mbps when transmitted at 260 Mbps of Physical Layer (PHY) data rate is obtained. This result is verified with X-X-IMPLEMENTATION on a Xilinx Field-Programmable Gate Array (FPGA) board.

With the growing demand for high-performance multimedia applications over wireless channels, we need to develop a Medium Access Control (MAC) system that supports high throughput and quality of service enhancements. This paper presents the standard analysis, design architecture and design issues leading to the implementation of an IEEE 802.11e based MAC system that supports MAC throughput of over 100 Mbps. In order to meet the MAC layer timing constraints, a hardware/software co-design approach is adopted. The proposed MAC architecture is implemented on the Xilinx Virtex-II Pro Field-Programmable Gate Array (FPGA) (XC2VP70-5FF1704C) prototype, and connected to a host computer through an external Universal Serial Bus (USB) interface. The total FPGA resource utilization is 11,508 out of 33,088 (34%) available slices. The measured MAC throughput is 100.7 Mbps and 109.2 Mbps for voice and video access categories, transmitted at a data rate of 260 Mbps based on IEEE 802.11n Physical Layer (PHY), using the contention-based hybrid coordination function channel access mechanism.

The Cuckoo Search (CS) is apt to be trapped in local optimum relating to complex target functions. This drawback has been recognized as the bottleneck of its widespread use. This paper, with the purpose of improving CS, puts forward a Cuckoo Search algorithm featuring Multi-Learning Strategies (LSCS). In LSCS, the Converted Learning Module, which features the Comprehensive Learning Strategy and Optimal Learning Strategy, tries to make a coordinated cooperation between exploration and exploitation, and the switching in this part is decided by the transition probability Pc. When the nest fails to be renewed after m iterations, the Elite Learning Perturbation Module provides extra diversity for the current nest, and it can avoid stagnation. The Boundary Handling Approach adjusted by Gauss map is utilized to reset the location of nest beyond the boundary. The proposed algorithm is evaluated by two different tests: Test Group A(ten simple unimodal and multimodal functions) and Test Group B(the CEC2013 test suite). Experiments results show that LSCS demonstrates significant advantages in terms of convergence speed and optimization capability in solving complex problems.