Test power has become a critical issue, especially for low-power devices with deeply optimized functional power profiles. Particularly, excessive capture power in at-speed scan testing may cause timing failures that result in test-induced yield loss. This has made capture-safety checking mandatory for test vectors. However, previous capture-safety checking metrics suffer from inadequate accuracy since they ignore the time relations among different transitions caused by a test vector in a circuit. This paper presents a novel metric called the Transition-Time-Relation-based (TTR) metric which takes transition time relations into consideration in capture-safety checking. Detailed analysis done on an industrial circuit has demonstrated the advantages of the TTR metric. Capture-safety checking with the TTR metric greatly improves the accuracy of test vector sign-off and low-capture-power test generation.

This paper describes a unified process and device simulation system named P &D Workbench (Process and Device Workbench). The P &D Workbench is an EWS (Engineering Work Station) based system which is connected with MFCs (Main Frame Computers) via networks and can easily execute 2-dimensional process, device, topography and capacitance simulations. Since the P &D Workbench has a supervisor, data-base and excellent user interface using Japanese menu functions and mouse operations, a handling time can be dramatically reduced. The supervisor controls the simulation sequence and file transfer, and manages jobs and files both on EWSs and MFCs, so that plural simulations of splitting conditions can be automatically executed. Short TAT (Turn Around Time) is achieved by selecting an appropriate platform depended on a problem size and MFCs' CPU loads. The effects of the P &D Workbench are shown in examples applied to the development of a 4M-DRAM.