This paper compares a stub and a decoupling capacitor for power supply noise reduction. A quarter-length stub attached to the power supply line of an LSI chip works as a band-eliminate filter, and suppresses the power supply bounce of the designed frequency. The conditions where the stub is more effective than the same-area decoupling capacitor are clarified. The stub will work more efficiently and on-chip integration will be possible on high frequency operation LSIs.

This paper proposes a high frequency resolution Digitally-Controlled Oscillator (DCO) using a single-period control bit switching scheme. The proposed scheme controls the tuning word of DCO in a single period for the fine frequency tuning. The LC type DCO is implemented to realize the proposed scheme, and is fabricated using a standard 65 nm CMOS technology. The measurement results show that the implemented DCO improves the frequency resolution from 560 kHz to 180 kHz without phase noise degradation with an additional area of 200 µm2.

This paper demonstrates an on-chip di/dt detector circuit. The di/dt detector circuit consists of a power supply line, an underlying spiral inductor and an amplifier. The mutual inductor induces a di/dt proportional voltage, and the amplifier amplifies and outputs the value. The measurement results show that the di/dt detector output and the voltage difference between a resistor have good agreement. The di/dt reduction by a decoupling capacitor is also measured using the di/dt detector.

This paper demonstrates a pulse width controlled PLL without using an LPF. A pulse width controlled oscillator accepts the PFD output where its pulse width controls the oscillation frequency. In the pulse width controlled oscillator, the input pulse width is converted into soft thermometer code through a time to soft thermometer code converter and the code controls the ring oscillator frequency. By using this scheme, our PLL realizes LPF-less as well as quantization noise free operation. The prototype chip achieves 60 µm 20 µm layout area using 65 nm CMOS technology along with 1.73 ps rms jitter while consuming 2.81 mW under a 1.2 V supply with 3.125 GHz output frequency.

This paper demonstrates a PLL compiler that generates the final GDSII data from a specification of input and output frequencies with PVT corner conditions. A Pulse Width Controlled PLLs (PWPLL) is composed of digital blocks, and thus suitable for being designed using a standard cell library and being layed out with a commercially available place-and-route (P&R) tool. A PWPLL has 8 design parameters. Our PLL compiler decides the 8 parameters and confirms the PLL operation with the following functions: 1) calculates rough parameter values based on an analytical model, 2) generates SPICE and gate-level verilog netlists with given parameter values, 3) runs SPICE simulations and analyzes the waveform, to examine the oscillation frequency or the voltage of specified nodes at a given time, 4) changes the parameter values to an appropriate direction depending on the waveform analyses to obtain the optimized parameter values, 5) generates scripts that can be used in commercial design tools and invokes the tools with the gate-level verilog netlist to get the final LVS/DRC-verified GDSII data from a P&R and a verification tools, and finally 6) generates the necessary characteristic summary sheets from the post-layout SPICE simulations extracted from the GDSII. Our compiler was applied to an 0.18µm standard CMOS technology to design a PLL with 600MHz output, 600/16MHz input frequency, and confirms the PLL operation with 1.2mW power and 85µm×85µm layout area.

This paper demonstrates a power supply noise reduction using on-board stubs. A quarter-length stub attached to the power supply line of an LSI chip works as a band-eliminate filter, and suppresses the power supply noise of the designed frequency. Preliminary experiments show that 87% of the designed frequency noise component is suppressed when stub patterns are written on a power supply area on a PCB board for a 1.25 GHz operating LSI. The results show the possibility of the stub on-chip integration when the operating frequency of LSIs becomes higher and the stub length becomes shorter.

This paper proposes an on-chip measurement method of PLL through fully digital interface. For the measurement of the PLL transfer function, we modulated the phase of the PLL input in triangular form using Digital-to-Time Converter (DTC) and read out the response by Time-to-Digital Converter (TDC). Combination of the DTC and TDC can obtain the transfer function of the PLL both in the magnitude domain and the phase domain. Since the DTC and TDC can be controlled and observed by digital signals, the measurement can be conducted without any high speed analog signal. Moreover, since the DTC and TDC can be designed symmetrically, the measurement method is robust against Process, Voltage, and Temperature (PVT) variations. At the same time, the employment of the TDC also enables a measurement of the PLL lock range by changing the division ratio of the divider. Two time domain circuits were designed using 180nm CMOS process and the HSPICE simulation results demonstrated the measurement of the transfer function and lock range.

This paper demonstrates a feedforward active substrate noise cancelling technique using a power supply di/dt detector. Since the substrate is usually tied with the ground line with a low impedance, the substrate noise is closely related to the ground bounce which is proportional to the di/dt when inductance is dominant on the ground line impedance. Our active cancelling detects the di/dt of the power supply, and injects an anti-phase current into the substrate so that the di/dt-proportional substrate noise is cancelled out. Our first trial shows that 34% substrate noise reduction is achieved on our test circuit, and the theoretical analysis shows that the optimized canceller design will enhance the substrate noise suppression ratio up to 56%.