A test structure to separately analyze the location where the hot-carrier-induced CMOSFET reliability is determined around the center or the isolation-edge along the channel-width was proposed and fabricated. The test structure has four kinds of MOSFETs; [A] and [D] MOSFETs with a short and a long channel-length all over the channel width, respectively, [B] MOSFET with the short and the long channel-length around the center and the both isolation-edges, respectively, and [C] MOSFET with the channel-length regions vice versa to the [B] MOSFET. The time dependent changes of the threshold voltages VT, the saturation currents IS, the linear currents IL and the maximum transconductances β up to 50,000 s were measured. All data for the wide channel-width MOSFETs were almost categorized into three; [A], [B]/[C] and [D]. The [B]/[C] data were well estimated from simple theoretical discussions by the combination of [A] and [D] data, which mean that the reliabilities are nearly the same around the center or the isolation-edge for the CMOSFETs.

A test structure to separately measure sheet resistances of highly-doped-drain (HDD) and lightly-doped-drain (LDD) in LDD-type CMOSFETs with various gate spaces S having sub-100 nm sidewalls was proposed. From the reciprocal of source/drain-resistance R-1 versus S characteristics, the sheet resistance ρH of the high-conductive-region (HCR) corresponding to HDD and the approximate width WLC of the low-conductive-region (LCR) corresponding to LDD could be estimated. Both of ρH and WLC for p- and n-MOS devices were scarcely dependent on the gate voltage. The sidewall-width difference of 40 nm could be sufficiently detected by using the test structure with the S pitch of about 60 nm. The R-1 versus S characteristics showed the unstable resistance variations in the narrow S region less than 0.3 µm, which corresponded to the minimum S for the process used for the test device fabrication and suggested that various micro-loading effects seriously affected on the characteristics.

The process mapping of the ALD process of HfO2 using HfCl4 and H2O is reported. A thickness uniformity better than 3% was achieved over a 300 mm-wafer at a deposition rate of 0.52 Å/cycle. Usually, H2O purge period is set less than 10 sec to obtain reasonable throughput; however, the amounts of residual impurities (Cl, H) found to be in the order of sub%, and these impurities are piled up near the HfO2/Si interface. In order to reduce the piled up impurities, we proposed a 2-step deposition in which purge period for initial 10-20 cycles was set to be 90 sec and that for remaining cycles was usual value of 7.5 sec. The leakage current is reduced to 1/10 by using this 2-step deposition.

There is increasing interest using CMOS circuits for highly integrated high frequency wireless telecommunications systems. This paper reviews recent works in transceiver architectures, circuits and devices technology for CMOS RFIC application. A number of practical problems those must be resolved in CMOS RFIC design are also discussed.

The electrical characteristics of sealed CMOSFETs with gates crossing sources/drains at 90 and 45 are experimentally investigated using test devices fabricated by an n-well CMOS process with trench isolation. Gain factors of surface-channel 90 and 45 n-MOSFETs can be estimated by a simple correction theory based on the combination of a center MOSFET and two edge MOSFETs. However, relatively large departures from the theory are observed in buried-channel 90 and 45 p-MOSFETs with widths less than the channel length. The difference between n- and p-MOSFETs is mainly due to the channel type. Other basic device parameters such as saturation drain currents, threshold voltages, subthreshold swings, maximum substrate currents and substrate-voltage dependence of threshold voltages are also measured and qualitatively explained.