We propose an integrated smart cable operation system and its architecture for the future cable network. In the proposed architecture, an application programs and various modules are loosely coupled using a cable operation system platform. We anticipate the task flows for the future optical cable network operation in order to realize the proposed system and architecture. Each task flow is broken down into "atomic tasks." The task flow can be changed easily by combining these atomic tasks. We use an object-oriented design for designing the cable operation system platform. As a first step towards the construction of the proposed system a pre-prototype system was constructed and the results are shown.

Mathematical morphology clarified geometrical properties of shape analysis algorithms for binary pictures. Results of labelling, distance transform, and adjacent numbering are, however, coded pictures. For full descriptions of shape analysis algorithms in the framework of mathematical morphology, it is necessary to extend morphological operations to code-labelled pictorial data. Nevertheless, extensions of morphology to code-labelled pictures have never discussed though the theory of gray morphology is well studied by several authors. Hence, this paper proposes a theory of the coded morphology which is based on the binary scaling of labels of pixels. The method uses n-layered binary sub-pictures for the processing of a picture with 2n labels. By introducing morphological operations for the coded point sets, we express some coding functions in the manner of the mathematical morphology. We also derive multidimensional array registers and gates which store and process coded pictures and morphological operations to them by proposing basic gates which compute parallelly logical operations for elements of Boolean layered arrays. These gates and registers are suitable for the implementation of the shape analysis processors on the three-dimensional VLSI and ULSI.

We describe an approach to describe moving pictures in terms of their structural properties for video editing, video indexing, and video coding. The description contains 2D shape, motion, spatial relation, and relative depth of each region. To obtain the description, we develop the incremental segmentation scheme which includes dynamic occlusion analysis to determine relative depths of several objects. The scheme has been designed along the analysis-by-synthesis" approach, and uses a sequence of images to estimate object boundaries and motion information successively/incrementally. The scheme consists of three components: motion estimation, prediction with dynamic occlusion analysis, and update of the segmentation results. By combining the information from extended (longer) image sequences, and also by treating the segmentation and dynamic occlusion analysis simultaneously, the scheme attempts to improve successively over time the accuracy of the object boundary and motion estimation.

This paper describes a method for describing a three-dimensional (3-D) scene by integrating color and range data. Range data is obtained by a feature-based stereo method developed in our laboratory. A color image is segmented into uniform color regions. A plane is fitted to the range data inside a segmented region. Regions are classified into three types based on the range data. A certain types of regions are merged and the others remain unless the region type is modified. The region type is modified if the range data on a plane are selected by removing of the some range data. As a result, the scene is represented by planar surfaces with homogeneous colors. Experimental results for real scenes are shown.

The construction of an optical subscriber loop and its operation system will be one of the most important infrastructures for the information society of the future. This paper presents a discussion of current and future service trends, the evolution of fiber-optic systems in the loop, and subscriber loop operation systems. Several operation technologies are also discussed which will enable the operation systems described in this paper to be constructed. Of these, the key technologies are an operation system architecture with flexibility, software technologies based on object-oriented design and programming, and automatic operation modules.

We propose a new type of Graph Rewriting Systems (GRS) that provide a theoretical foundation for using the reduction method which plays an important role on analyze network reliability. By introducing this GRS, several facts were obtained as follows: (1) We clarified the reduction methods of network reliability analysis in the theoretical framework of GRS. (2) In the framework of GRS, we clarified the significance of the completeness in the reduction methods. (3) A procedure of recognizing complete systems from only given rewriting rules was shown. Specially the procedure (3) is given by introducing a boundary graph (B-Graph). Finally an application of GRS to network reliability analysis is shown.

A method for the recognition of Arabic printed scripts entered from an image scanner is presented. The method uses the Hough transformation (HT) to extract features, Dynamic programming (DP) matching technique, and a topological classifier to recognize the characters. A process of characters recognition is further divided into four parts: preprocessing, segmentation of a word into characters, features extraction, and characters identification. The preprocessing consists of the following steps: smoothing to remove noise, baseline drift correction by using HT, and lines separation by making an horizontal projection profile. After preprocessing, Arabic printed words are segmented into characters by analysing the vertical and the horizontal projection profiles using a threshold. The character or stroke obtained from the segmentation process is normalized in size, then thinned to provide it skeleton from which features are extracted. As in the procedure of straight lines detection, a threshold is applied to every cell and those cells whose count is greater than the threshold are selected. The coordinates (R, θ) of the selected cells are the extracted features. Next, characters are classified in two steps: In the first one, the character main body is classified using DP matching technique, and features selected in the HT space. In the second one, simple topological features extracted from the geometry of the stress marks are used by the topological classifier to completely recognize the characters. The topological features used to classify each type of the stress mark are the width, the height, and the number of black pixels of the stress marks. Knowing both the main group of the character body and the type of the stress mark (if any), the character is completely identified.

In this paper, a new scheme for ohrase recognition in conversational speech is proposed, in which prosodic and phonemic information processing are usefully combined. This approach is employed both to produce candidates of phrase boundaries and to discriminate phonemes. The fundamental frequency patterns of continuous utterances are statistically analyzed and the likelihood of the occurrence of a phrase boundary is calculated for every frame. At the same time, the likelihood of phonemic characteristics of each frame can be obtained using a hierarchical clustering method. These two scores, along with lexical and grammatical constraints, can be effectively utilized to develop a possible word sequences or a word lattices which correspond to the continuous speech utterances. Our preliminary experjment shows the feasibility of applying prosody for continuous speech recognition especially for conversational style utterances.

A detailed numerical solution of the design criteria of in-phase lateral and single-longitudinal-mode operation GaInAsP/InP DFB laser arrays is presented. The analysis, including broad-area pumped and stripe-geometry pumped index-guided arrays, was carried out on the basis of the eigenvalue equation method. It is shown that there exists a cut-off array pitch co, at which all of the higher-order array modes are cut off. For the pitch larger than the cut-off pitch co, the modal discrimination is evaluated by the threshold gain difference between the in-phase lateral and higher-order array modes. As a result, the modal discrimination was found to decrease with the increase of the number of elements and the array pitch which is limited to be smaller than twice the cut-off pitch co to attain a stable in-phase lateral- and single-longitudinal-mode operation.

This paper describes a new method for verifying designs at the RTL with respect to their specifications at the functional level. The base of the verification method shown here is the translation of the specification and design representations to graph models, where the descriptions common to both representations have a symbolic representation. These symbol labeled graphs are then simplified and, by solving the all node-pair path expression problem for them, a pair of regular expressions is obtained for every two nodes in the graphs. The first regular expression in each pair represents the flow of control and the second one the flow of data between the corresponding nodes. The process of verification is carried out by checking whether or not every pair of regular expressions of the specification has a corresponding pair in the design.

In developing the SXO operating system for the SURE SYSTEM 2000 continuous operation system, we aimed to create an unprecedentedly high software and hardware fault tolerance. We devised a fault tolerant architecture and various methodologies to ensure fault tolerance. We implemented these techniques systematically throughout operating system development. In the design stage, we developed a design methodology called the recovery process chart to verify that recovery mechanisms were complete. In the manufacturing stage, we applied the concept of critical routes to recovery and other processes essential to high dependability. We also developed a method of finding critical routes in a recovery process chart. In the test stage, we added an artificial software fault injection mechanism to the operating system. It generates various reproducible errors at appropriate times and reduces the number of personnel needed for test, making system reliability evaluation easy.

This paper describes a computer-aided service creation environment (CSCE) for the intelligent network which supports easier graphical specification description for service designers of various skill levels, and service logic program (SLP) generation. The CSCE design concept consists of stepwise service specification description and SLP generation, message sequence chart description language (LSDL: Layered Service Specification Description Language), computer-aided sophisticated interface (IEDs: Intelligent Editors), automatic specification verification and rapid service prototyping. Service specification is described by three steps and in LSDL or SDL, and SLPs are generated through three converters referring to two knowledge databases. Three tests are conducted on the specifications described. The effectiveness of the CSCE is demonstrated by the results that the amount of SLP descriptions for five new practical services using the CSCE is reduced to less than about 20% in LSDL description, compared to C language description.

A conflict detection support method for combining additional telecommunication services with existing services is proposed. In this method, telecommunication services are described by the STR (State Transition Rule) method which specifies a set of state transition rules. Though conflict detection in the past depended on manual analysis by the designer, with this method, conflict candidates are mechanically narrowed down and indicated to the designer. All conflicts between five actual telecommunication service descriptions are detected in an experiment using a system developed in line with the proposed method.

This paper describes a verification scheme for service specifications and presents verification results for prototype system. Verified specifications are described by information sequence charts, which describe the communicating states between users and the messages between a user and a network. The verification scheme consists of two steps: macro sequence verification, which treats rough transitions of states, and transition procedure verification, which treats procedure of all messages. A prototype verification system demonstrates that this scheme can detect about 90% of errors in a specification within 4.4 seconds.

Fiber-optic subscriber loops are beginning to be constructed worldwide as an infrastructure for the 21st century. Making the most of the superior transmission capabilities of optical fiber cable, high-speed and broadband services such as so-called Broadband-ISDN (B-ISDN) services are expected to be achieved. We review current trends in fiber-optic systems and discuss how fiber-optic subscriber loops should be implemented from the points of view of services and technology. First, prospective services offered over fiber-optic subscriber loops and resulting requirements for such loops are presented. Various kinds of services produced through fiber-optic subscriber loops will further develop the information-oriented society and have a major influence not only on the industrial world but on family life as well. Next, basic concepts of totally fiber-optic subscriber loops and proposals for shifting from the existing metallic cable network to totally fiber-optic subscriber loops are discussed. In this regard, we must consider the advantages of optical fiber cables and improve upon the disadvantages of the existing metallic cable network. In particular, a Digital Loop Carrier (DLC) system or a Passive Double Star (PDS) have been proposed to shift from the existing metallic cable network to totally fiber-optic subscriber loops effectively and economically. Finally, line configuration topology and latest fiber-optic technologies such as high-count cable, construction techniques and operation systems for use in achieving totally fiber optic subscriber loops are shown. We believe a single star configuration is the most appropriate for totally fiber-optic subscriber loops.

This article proposes, given an independently-and-identically distributed binary source, an arithmetic code-like variable-to-variable length source code whose compression efficiency achieves nearly the rate function in a range of small distortion. Inheriting advantages of arithmetic codes, the proposed code requires neither large memory capacity nor large computation time for management of messages and codewords. The Elias code, which can be regarded as an antecedent of arithmetic codes, is defined originally in terms of the first-in-first-out (FIFO) coding form. The proposed code corresponds to an extension from the Elias code refined in terms of the last-in-first-out (LIFO) coding form into one considered a fidelity criterion.

Experimental results on the superconducting three-terminal devices Using Bi-system High-Tc Superconductors were reported. The VCJJ (Variabel critical-current-type Josephson junction devices) using the thermal effect (VCJJ) and a dual gate Josephson device of a new current-injection type are described. The basic technology and problems for high-Tc three-terminal devices are briefly discussed.

This paper designs and evaluates highly parallel VLSI processors for real time 2-D state-space digital filters using hierarchical behavioral description language and synthesizer. The architecture of the 2-D state-space digital filtering system is a linear systolic array of homogeneous VLSI processors, each of which consists of eight processing elements (PEs) executing 1-D state-space digital filtering with multi-input and multi-output. Hierarchical behavioral description language and synthesizer are adopted to design and evaluate PE's and the VLSI processors. One 16 bit fixed-point PE executing a (4, 4)-th order 2-D state-space digital filtering is described on the basis of distributed arithmetic in about 1,200 steps by the description language and is composed of 15 K gates in terms of 2 input NAND gate. One VLSI processor which is a cascade connection of eight PEs is composed of 129 K gates and can be integrated into one 1515 [mm2] VLSI chip using 1 µm CMOS standard cell. The 2-D state-space digital filtering system composed of 128 VLSI processors at 25 MHz clock can execute a 1,0241,024 image in 1.47 [msec] and thus can be applied to real-time conventional video signal processing.

Based on the Fornasini-Marchesini second model, an efficient algorithm is developed to derive the characteristic polynomial and the inverse of the system matrix from the state-space parameters. As a result, the external description of the Fornasini-Marchesini second model is clarified. A technique for designing 2-D recursive digital filters in the frequency domain is then presented by using the Fornasini-Marchesini second model. The resulting filter approximates both magnitude and group delay specifications and its stability is always guaranteed. Finally, three design examples are given to illustrate the utility of the proposed technique.

This paper describes a method of evaluating operations effort for fiber optic subscriber loops, such as the Central Terminal/Remote Terminal (CT/RT) system, which can economically provide a variety of telecommunication services. Four system configurations with different operation procedures are evaluated by simulation. By evaluating the operating costs associated with service provisioning, it is shown that automatic distributing frames are cost effective in subscriber loops with CT/RT systems. Moreover, the most economical operation strategies for installing and extending subscriber boards are discussed in terms of facility and operations cost.