1-3hit |
Ji-Hun EO Yeon-Ho JEONG Young-Chan JANG
An 8-bit 100-kS/s successive approximation (SA) analog-to-digital converter (ADC) is proposed for measuring EEG and MEG signals in an 88 point. The architectures of a SA ADC with a single-ended analog input and a split-capacitor-based digital-to-analog converter (SC-DAC) are used to reduce the power consumption and chip area of the entire ADC. The proposed SA ADC uses a time-domain comparator that has an input offset self-calibration circuit. It also includes a serial output interface to support a daisy channel that reduces the number of channels for the multi-point sensor interface. It is designed by using a 0.35-µm 1-poly 6-metal CMOS process with a 3.3 V supply to implement together with a conventional analog circuit such as a low-noise-amplifier. The measured DNL and INL of the SA ADC are +0.63/-0.46 and +0.46/-0.51 LSB, respectively. The SNDR is 48.39 dB for a 1.11 kHz analog input signal at a sampling rate of 100 kS/s. The power consumption and core area are 38.71 µW and 0.059 mm2, respectively.
Yanli WAN Zhenjiang MIAO Zhen TANG Lili WAN Zhe WANG
This letter proposes an efficient local descriptor for wide-baseline dense matching. It improves the existing Daisy descriptor by combining intensity-based Haar wavelet response with a new color-based ratio model. The color ratio model is invariant to changes of viewing direction, object geometry, and the direction, intensity and spectral power distribution of the illumination. The experiments show that our descriptor has high discriminative power and robustness.
Kiichi NIITSU Noriyuki MIURA Mari INOUE Yoshihiro NAKAGAWA Masamoto TAGO Masayuki MIZUNO Takayasu SAKURAI Tadahiro KURODA
A daisy chain of current-driven transmitters in inductive-coupling complementary metal oxide semiconductor (CMOS) links is presented. Transmitter power can be reduced since current is reused by multiple transmitters. Eight transceivers are arranged with a pitch of 20 µm in 0.18 µm CMOS. Transmitter power is reduced by 35% without sacrificing either the data rate (1 Gb/s/ch) or BER (<10-12) by using a 4-transmitter daisy chain. A coding technique for efficient use of daisy chain transmitters is also proposed. With the proposed coding technique, additional power reduction can be achieved.