We present a new apparent bandgap narrowing model for semiconductor device simulation. The new model is derived from revised data of previous measurements on the apparent bandgap narrowing by using a corrected intrinsic carrier concentration. The revised values reveal sufficient agreement with our theoretical calculation. The new model is implemented in a triangular mesh device simulator TRIMEDES. Simulated BJT current-voltage and current-temperature characteristics using the proposed model reveal excellent agreement with measurements.

We have developed an efficient general-purpose two-dimensional device simulation system which consists of a solver, and pre- and post-processors. This system can easily handle any complicated device having a non-rectangular shape. It can also be applied to compound semiconductor devices with heterojunctions, including optical devices such as laser diodes. In order to handle any device, a new program for construction of device geometry is developed as a preprocessor. It has an efficient graphic interface to reduce the time required to input data for simulations, which is a very time consuming task for complicated devices. A new efficient data structure representing device geometry is introduced in the program. During postprocessing, any physical quantity can be displayed on the multi-window screen. In addition, a general-purpose solver for basic semiconductor equations is implemented in the system. Using this system, any device can be successfully analyzed in a unified manner and the turn-around time for the simulation is significantly reduced.

In this paper, a "hydrodynamic" version of the three-dimensional code HFIELDS-3D is used to achieve a detailed knowledge on the distribution of the substrate current inside a recessed-oxide MOSFET. The physical model features a temperature-dependent formulation of the impact-ionization rate, allowing non-local effects to be accounted for. The discretization strategy relies on the Box Integration scheme and uses suitable generalizations of the Scharfetter-Gummel technique for the energy-balance equation. The simulation results show that the narrow-channel effect has a different impact on drain and substrate currents. Further three-dimensional effects, such as the extra heating of the carriers at the channel edge, are demonstrated.

An automatic optimization system for semiconductor devices has been built-up by fully interfacing an optimizer and a device-analysis code supplemented with sensitivity analysis. The device-analysis code is thought of as a part of a pipeline of simulators. The latters are regarded as subprocesses by the optimizer, which controls their I/O stream. The action of the pipeline is iterated until the optimum set of design parameters is determined. An important feature of the system is that all the derivatives required in the sensitivity analysis are calculated analytically, this providing a substantial improvement in both the numerical accuracy and computational efficiency, and making the scheme attractive from the application standpoint. A few examples of optimization of MOS devices are shown and the performance is reported, indicating that a system of this kind can usefully be exploited in a design environment.

A rigorous theoretical method for predicting "ratio of desired signal power to interference power [c/i]" and "ratio of signal power to noise plus interference power [c/(n+i)]" where both desired and interference signals vary with time under the Nakagami-Rice fading conditions is presented. An alternative simple prediction method which is more desirable from the viewpoint of engineering application is then proposed. Prediction errors given by the simple method are evaluated by comparing to the errors given by the rigorous method, and it is confirmed that the simple method gives reasonable accuracy. This method is expected to serve in the development of frequency re-use technologies and the coordination of various systems for mobile satellite communications in the near future.

The VSTEP concept and its practical application in the form of an LED-type pnpn-VSTEP demonstrating low power consumption through electro-photonic operational modes are both shown. Further, with focus primarily on the new laser-mode VSTEP with high-intensity light output and narrow optical beam divergence, the design features such as threshold gain and optical absorptivity, device fabrication, and characteristics are explained. The possibility of ultimate performance based mainly on electrical to optical power conversion efficiency, important from the application viewpoint of optical interconnection, are also discussed. Also, as two examples of functional optical interconnection achieved by VSTEP, serial-to-parallel data conversion and optical self-routing switches are shown. Finally, future opto-electronic technologies to be developed for two-dimensionally integrable surface-type optical semiconductor devices, including the VSTEP, are discussed.

The VSTEP concept and its practical application in the form of an LED-type pnpn-VSTEP demonstrating low power consumption through electro-photonic operational modes are both shown. Further, with focus primarily on the new laser-mode VSTEP with high-intensity light output and narrow optical beam divergence, the design features such as threshold gain and optical absorptivity, device fabrication, and characteristics are explained. The possibility of ultimate performance based mainly on electrical to optical power conversion efficiency, important from the application viewpoint of optical interconnection, are also discussed. Also, as two examples of functional optical interconnection achieved by VSTEP, serial-to-parallel data conversion and optical self-routing switches are shown. Finally, future opto-electronic technologies to be developed for two-dimensionally integrable surface-type optical semiconductor devices, including the VSTEP, are discussed.