Ternary content addressable memory (TCAM) is becoming very popular for designing high-throughput forwarding engines on routers. However, TCAM has potential problems in terms of hardware and power costs, which limits its ability to deploy large amounts of capacity in IP routers. In this paper, we propose new hardware architecture for fast forwarding engines, called fast prefix search RAM-based hardware (FPS-RAM). We designed FPS-RAM hardware with the intent of maintaining the same search performance and physical user interface as TCAM because our objective is to replace the TCAM in the market. Our RAM-based hardware architecture is completely different from that of TCAM and has dramatically reduced the costs and power consumption to 62% and 52%, respectively. We implemented FPS-RAM on an FPGA to examine its lookup operation.

Ternary Content Addressable Memory (TCAM) is a special type of memory used in routers to achieve high-speed packet forwarding and classification. Packet forwarding is done by referring to the rules written in the routing table, whereas packet classification is performed by referring to the rules in the Access Control List (ACL). TCAM uses more transistors than Random Access Memory (RAM), resulting in high power consumption and high production cost. Therefore, it is necessary to reduce the entries written in the TCAM to reduce the transistor count. In this paper, we propose a new TCAM architecture by using Range Matching Devices (RMD) integrated within the TCAM's control logic with an optimized prefix expansion algorithm. The proposed method reduces the number of entries required to express ACL rules, especially when specifying port ranges. With less than 10 RMDs, the total number of lines required to write port ranges in the TCAM can be reduced to approximately 50%.

To guarantee strict Quality of Service (QoS) for real-time applications, we have previously proposed an output buffer control mechanism in IP routers, confirmed its effectiveness through simulations, and implemented a prototype. This mechanism can guarantee strict QoS within a single router. In this paper, we propose a control scheme of cooperation between IP routers equipped with this mechanism by using one of the signaling protocols. Our proposed scheme aims to stabilize End-to-End (E2E) flow delay within the target delay. In addition, our mechanism dynamically updates reserved resources between IP routers to improve E2E packet loss rate. We present an implemented design of our scheme and an empirical evaluation of the implementation. These results show quantitatively how our scheme improves the quality of video pictures.

In this paper, we propose a protocol for multicast communication called Multicast Datagram Transfer Protocol (MDTP) to provide multicast for video broadcasting service on the Internet. MDTP is a one-to-many multicast communication protocol, which is constructed based on IPv4 unicast protocol by utilizing IP Router Alert Option, and it uses unicast addressing and unicast routing protocol. A mechanism is presented to allow a router to remove identical video stream, to duplicate a video stream, and to forward each copy of the duplicated video stream to its destinations. Ordinary IP routers that do not support MDTP will treat the MDTP packets as normal unicast packets. Hence, gradual deployment is possible without tunneling technique. With a delegation mechanism, MDTP router is also able to handle request from clients, and serve the requested video stream. The simulation results show that the average bandwidth usage of MDTP is close to the average bandwidth usage of IP multicast. MDTP also has greater efficiency than XCAST, and its efficiency becomes significant for a large number of clients.

The growth in the volume of Internet traffic and the increasing variety of Internet applications require Internet backbone networks to be scalable and provided sophisticated quality of service (QoS) capabilities. Internet backbone routers have evolved to achieve sub-Tbps switching capacity in a single unit, but their switch architectures have limited scalability, causing QoS to degrade as the switches get bigger. Hence, we propose a large-scale IP and lambda integrated router architecture with scalable switches. We first describe the system architecture of our proposed backbone router and clarify the requirements for its switching capabilities to meet near-future demands. The new switch architecture, using crossbar-based switching fabrics and optical interconnection devices, meets the requirements for a backbone router to scale up to 82 Tbps and enable light path switching as well as packet switching. The routing tag and its usage algorithm in the switch, and packaging issues, including the quantity of hardware required for expansion, are also discussed.