In an ATM network, there are quality impairments particular to the ATM network such as cell loss and delay variation. During ATM network planning, therefore, various causes of quality impairments should be clarified. This paper overviews ATM network performance issues, and discusses performance requirements for the SDH network which will be applied as a physical layer of the ATM network. It also presents ATM network performance planning methods on cell loss and cell delay.

This paper describes the configuration and performance of a stable, high compression video coding scheme suitable for broadcast quality. This scheme was developed for application to high quality image packet transmission in Asynchronous Transfer Mode (ATM) networks. There are two problems in implementing image packet transmission in ATM networks, namely the achievement of a compression scheme with high coding efficiency, and the achievement of an effective compensation method for cell loss. We describe a scheme which resolves both these problems. It comprises the division of a two-dimensional spectral image signal into several sub-bands. In the case of the high frequency band, block-matching interframe prediction and Discrete Cosine Transform (DCT) are applied to achieve high compression ratio, while intraframe DCT coding is applied to the baseband. This scheme, moreover, provides a stable compensation for cell loss. It is shown that, based on this system, an original image signal of 216Mbit/s is compressed to about 1/10, and a high quality reconstructed image stable to cell loss is obtained.

A fully integrated digital PLL (Phase Locked Loop) with on-chip CMOS oscillator is described. Nominal division number of the variable divider is automatically tuned in this digital PLL and this feature makes it possible to widen the pull-in range. In general, output jitter may increase if the pull-in range is widened. To overcome this problem, output jitter is reduced by utilizing the dual loop architecture. Wide pull-in range enables us on-chip oscillator, which is not so precise as the expensive crystal oscillator. This CMOS oscillator must be carefully designed to be stable against the temperature and the supply voltage variations. Using these digital PLL techniques, together with the on-chip CMOS oscillator, a fully integrated PLL can be achieved. Circuits are designed for 1.544 Mbit/s ISDN primary rate interface, and 6.25% pull-in range is obtained.

One performance limitation of the "Leaky Bucket algorithm" for usage parameter control and traffic management in Asynchronous Transfer Mode (ATM) networks is analyzed. Simulation results show that the conventional statistical bandwidth allocation method, which uses the most bursty pattern permitted by the Leaky Bucket algorithm, can not guarantee the QOS of established Virtual Channels/Paths (VC/VP). As a result, the VC/VP bandwidth allocation method based on the Leaky Bucket algorithm is proven to be unsatisfactory.

Electromagnetic interference on a bus wiring configuration of the ISDN basic interface using metallic telecommunication lines is studied. A simple circuit to simulate terminal equipment unbalance about earth is developed for measurement purposes, based on the fact that the unbalance weakens the withstanding capability against interference. The electromagnetic interferences from low-voltage supply lines, analog telephone lines and broadcasting waves are evaluated by experiments using the circuit. The interference is measured by both induced voltage on the interface line and the error rate of the transmission signal line. Consequently, it is clarified that the basic interface is disturbed by the induced voltage, because the terminal equipment in the CCITT Recommendation I.430 has too large an unbalance about earth to maintain transmission quality. Adding to this, countermeasures to reduce interference are proposed.