In this letter, a theoretical analysis of bit error probability for 4-state convolutional code with Max-Log-maximum a posteriori probability (MAP) decoding is presented. This technique employs an iterative calculation of probability density function of the state metric per one transition, and gives the exact bit error probability for all signal-to-noise power ratio.

An improved Max-Log-Map (MLM) turbo equalization algorithm called Scaled Max-Log-Map (SMLM) iterative equalization is presented. Simulations show that the scheme can dramatically outperform the MLM besides it is insensitive to SNR mismatch. Unfortunately, its performance is still much worse than that of Log-Map (LM) with exact SNR over high-loss channels. Accordingly, we also propose a new SNR estimation algorithm based on the reliability values of soft output extrinsic information of SMLM decoder. Using the new scheme, we obtain good performance close to that of LM with ideal knowledge of SNR.

As turbo decoding is a highly memory-intensive algorithm consuming large power, a major issue to be solved in practical implementation is to reduce power consumption. This paper presents an efficient reverse calculation method to lower the power consumption by reducing the number of memory accesses required in turbo decoding. The reverse calculation method is proposed for the Max-log-MAP algorithm, and it is combined with a scaling technique to achieve a new decoding algorithm, called hybrid log-MAP, that results in a similar BER performance to the log-MAP algorithm. For the W-CDMA standard, experimental results show that 80% of memory accesses are reduced through the proposed reverse calculation method. A hybrid log-MAP turbo decoder based on the proposed reverse calculation reduces power consumption and memory size by 34.4% and 39.2%, respectively.

Thanks to the possibility of being able to implement them in decoders in relatively simple ways, turbo codes are being applied to various areas of engineering. Wireless communications is one of the most important applications, where various types of data communications are required and the speed of information and data capacity need to be changed with different rates of parity bit puncturing being adopted to obtain highly efficient transmission. In such applications, adaptation to various turbo-coding specifications on a real-time basis is needed as well as good bit-error-rate performance. We present a new concept for simplifying metric computation and programmable circuit configurations that focuses on the convolutional decoder, which occupies a significant portion of allocated hardware, and we fundamentally treat a simplified log-domain version of the maximum a posteriori (MAP) algorithm, usually know as the Max-Log-MAP (MLM), as a base algorithm. The sliding window method provides an attractive way of computing metric values for the Max-Log-MAP. However, this algorithm does cause degradation, especially when a high rate code is used, generated by bit puncturing. We propose a new means of avoiding this problem and demonstrate that the sliding window, and a modified version as well as other methods, should be flexibly selected to utilize hardware resources depending on turbo specifications. We demonstrated that our proposed methods provide almost the same BER performance as MLM even when a high rate puncturing rate of 5/6 is applied. Finally, we describe the new hardware architecture that we invented to cope with these programmability issues. We show that a turbo-decoding circuit can be implemented in the processor core and its associated unit to configure an LSI macro circuit. The proposed unit has about 60-K gates. We demonstrate that this architecture can be applied to about the 1.5-Mbps information bit throughput of turbo decoding with a 200-MHz clock cycle, which is achievable with today's advanced CMOS technologies.

The maximum a posteriori (MAP) algorithm is the optimum solution for decoding concatenated codes, such as turbo codes. Since the MAP algorithm is computationally complex, more efficient algorithms, such as the Max-Log-MAP algorithm and the soft-output Viterbi algorithm (SOVA), can be used as suboptimum solutions. Especially, the Max-Log-MAP algorithm is widely used, due to its near-optimum performance and lower complexity compared with the MAP algorithm. In this paper, we propose an efficient algorithm for decoding concatenated codes by modifying the Max-Log-MAP algorithm. The efficient implementation of the backward recursion and the log-likelihood ratio (LLR) update in the proposed algorithm improves its computational efficiency. Memory is utilized more efficiently if the sliding window algorithm is adopted. Computer simulations and analysis show that the proposed algorithm requires a considerably lower number of computations compared with the Max-Log-MAP algorithm, while providing the same overall performance.

Turbo codes are of particular use in applications of wireless communication systems, where various types of communication are required and the data rate must be changed, depending on the situation. In such applications, adaptation of turbo coding specifications is required in terms of coding block size, data speed, parity bit arrangement or configuration of a convolutional coder, as well as the need for real time processing. We present new ideas to provide these capabilities for a low power decoder circuit by focusing on the configuration of a convolutional decoding algorithm, which occupies a significant proportion of the hardware circuit. We utilize the Soft Output Viterbi Algorithm (SOVA) for the base algorithm, produced by adding the concept of a soft output to the Viterbi Algorithm (VA). The Maximum A Posteriori (MAP) algorithm and its simplified version of MAX-LOG-MAP are also widely known. MAP is recognized as a means of achieving very good bit error rate (BER) characteristics. On the other hand SOVA has been regarded as a method which can be simply implemented with less computational resources, but at a cost of higher degradation. However, in many of recent systems we combine turbo coding with some other method such as Automatic Repeat Request (ARQ) to maintain a good error correction performance and we only have to pay attention to the performance in the range of low carrier-to-noise ratio (CNR), where SOVA has fairly satisfactory BER characteristics. This makes the SOVA approach attractive for a low power programmable IP macro solution, when the fundamental advantage of SOVA is fully utilized in the implementation of an LSI circuit. We discuss the processing algorithm and circuit configuration and show that about 40% reduction in power consumption can be achieved. It is also shown that the IP macro can handle 1.5 Mbps information decoding at 100 MHz clock rate.

Serious BER performance degradation due to finite numeric precision in VLSI implementation of Log-MAP and MAX-Log-MAP decoders where forward state metric is calculated using reverse tracing method, is analyzed, and two methods are proposed to overcome this problem, the loser storing method for MAX-Log-MAP and the periodic storing method for Log-MAP and MAX-Log-MAP. Both methods can reduce memory storage size effectively by half, but with additional circuit overhead. Our VLSI implementation examples show that, compared with original method, both methods give about 15% improvement in area and power consumption with identical BER performance.

Several implementation methods for a MAP decoder are proposed in this paper. Using a novel pipeline structured time-shared process, the authors are able to efficiently overcome the restrictions imposed by the recursion process on state metrics, and the complexity of the MAP decoder can be reduced to a level on the order of a SOVA (Soft Output Viterbi Algorithm) decoder. In addition, the authors propose an efficient controller structure that can be used for variable frame-size systems such as cdma-2000. The MAP decoder using a block-wise algorithm designed here was implemented in only one 20,000 gate circuit. It was validated by VHDL, which was compared with the results of the initial simulation (C programs). The decoder demonstrated a 300 kbps decoding processing ability with 8 iterations on a FPGA circuit, with a deviation only about 0.1-0.2 dB greater than that for an ideal MAP decoder, even when all hardware environments are considered.