Hiroshi MATSUURA Naotaka MORITA Tatsuro MURAKAMI Kazumasa TAKAMI
Multilayered network interaction among various networks such as IP/MPLS packet networks and optical fiber networks are now achieved using generalized multiprotocol label switching (GMPLS) technology. One unique feature of GMPLS networks is that GMPLS packet-layer label switching paths (LSPs), such as IP/MPLS LSPs, sometimes tunnel through GMPLS lower layer LSPs such as optical fiber/lambda LSPs. One problem that occurs in this situation is protecting an important primary packet LSP by using a protection LSP that is physically separated from the primary LSP. The packet router has difficulty recognizing lower layer LSPs that are totally disjointed from the primary LSP. This is because, in a GMPLS's packet layer, a source router only differentiates one lower layer LSP from another, and does not check the disjointedness of segments through which the lower layer path passes. Sometimes, different lower LSPs pass through the same optical fiber, and a malfunction of one optical fiber sometimes causes many lower layer LSPs to malfunction at the same time. To solve this problem, a shared risk link group (SRLG) is introduced. Network links that belong to the same SRLG share a common physical resource. We apply this SRLG to the proposed hierarchically distributed path computation elements (HDPCEs) and achieve effective disjointed SRLG protection for important primary GMPLS packet paths.
This letter proposes a robust detection scheme of orthogonal space-time block codes that face very fast fading channels. The proposed detection scheme employs a QR decomposition on the channel matrix and minimizes noise enhancement and impact of channel estimation errors which occur in a conventional detection scheme. It is shown by simulations that the proposed detection scheme outperforms the conventional detection scheme when the channel fading is very fast.
Yuanyuan ZHANG Wei SUN Yasushi INOGUCHI
To make the best use of the resources in a shared grid environment, an application scheduler must make a prediction of available performance on each resource. In this paper, we examine the problem of predicting available CPU performance in time-shared grid system. We present and evaluate a new and innovative method to predict the one-step-ahead CPU load in a grid. Our prediction strategy forecasts the future CPU load based on the variety tendency in several past steps and in previous similar patterns, and uses a polynomial fitting method. Our experimental results on large load traces collected from four different kinds of machines demonstrate that this new prediction strategy achieves average prediction errors which are between 22% and 86% less than those incurred by four previous methods.
Taiji SASAOKA Hideyuki KAWABATA Toshiaki KITAMURA
Parallel programs for distributed memory machines are not easy to create and maintain, especially when they involve sparse matrix computations. In this paper, we propose a program translation system for generating parallel sparse matrix computation codes utilizing PSBLAS. The purpose of the development of the system is to offer the user a convenient way to construct parallel sparse code based on PSBLAS. The system is build up on the idea of bridging the gap between the easy-to-read program representations and highly-tuned parallel executables based on existing parallel sparse matrix computation libraries. The system accepts a MATLAB program with annotations and generates subroutines for an SPMD-style parallel program which runs on distributed-memory machines. Experimental results on parallel machines show that the prototype of our system can generate fairly efficient PSBLAS codes for simple applications such as CG and Bi-CGSTAB programs.
This letter develops an efficient CPM demodulator which provides soft outputs for use in coded CPM. The proposed algorithm offers reduced-complexity soft output detection in which the number of matched filters and trellis states is appreciably reduced. The complexity reduction is achieved by approximating the CPM signal using the Laurent representation. A simulation study of iterative decoding of serially concatenated CPM with an outer code was performed. The performance degradation of the proposed algorithm relative to optimal full complexity generation of soft outputs was found to be small.
Satoshi NAKAYAMA Maki YOSHIDA Shingo OKAMURA Toru FUJIWARA
Data retrieval is used to obtain a particular data item from a database. A user requests an item in the database from a database server by sending a query, and obtains the item from an answer to the query. Security requirements of data retrieval include protecting the privacy of the user, the secrecy of the database, and the consistency of answers. In this paper, a data retrieval scheme which satisfies all the security requirements is defined and an efficient construction is proposed. In the proposed construction, the size of a query and an answer is O((log N)2), and the size of data published by the database server when the database is updated is only O(1). The proposed construction uses the Merkle tree, a commitment scheme, and Oblivious Transfer. The proof of the security is given under the assumption that the used cryptographic schemes are secure.
Seiichiro NAKABAYASHI Nobuko TANIMURA Toshikazu YAMASHITA Shinichiro KOKUBUN
The relationship between the topology and collective function of a nonlinear oscillator network was investigated using nonlinear electrochemical oscillators. The constitutive experiments showed that the physiological robustness in the living system is due to their topological redundancy and asymmetry in the nonlinear network.
Katsuyuki HAGIWARA Hiroshi ISHITANI
In this article, we considered the asymptotic expectations of the prediction error and the fitting error of a regression model, in which the component functions are chosen from a finite set of orthogonal functions. Under the least squares estimation, we showed that the asymptotic bias in estimating the prediction error based on the fitting error includes the true number of components, which is essentially unknown in practical applications. On the other hand, under a suitable shrinkage method, we showed that an asymptotically unbiased estimate of the prediction error is given by the fitting error plus a known term except the noise variance.
Hyung-Hoon KIM Saehoon JU Seungwon CHOI Jong-Il PARK Hyeongdong KIM
To make the best use of the known characteristics of the alternating-direction-implicit finite-difference time-domain (ADI-FDTD) method such as unconditional stability and modeling accuracy, an efficient time domain solution with variable time-step size is proposed. Numerical results show that a time-step size for a given mesh size can be increased preserving a desired numerical accuracy over frequencies of interest.
Sergei BYCHENKOV Vladimir MIKHAILOV Kohichi SAKANIWA
DS-CDMA systems employing long-period PN sequences are becoming a widespread standard of wireless communication systems. However, fast acquisition of long-period PN sequences at a low hardware cost is conventionally a difficult problem. This paper examines a recently proposed fast acquisition algorithm for a class of PN sequences, which includes m and GMW sequences as special cases, under conditions of unknown received RF phase and chip boundary timing. The result shows that under low input (chip) SNR and the required delay estimation accuracy of Tc/Δ, Δ=2,3,…, the mean acquisition time can be considerably reduced compared to other known representative acquisition schemes. Its fast acquisition capability is based on a decomposition of long PN sequences into a number of short ones and achieves a significantly reduced code phase uncertainty of acquisition at relatively small hardware cost, estimated as 2/3 of the equivalent parallel correlators system. It can be applied as a (part of) acquisition scheme of a DS-CDMA system instead of a slow sliding correlator or a costly matched filter schemes.
Hiroki NAKAHARA Tsutomu SASAO Munehiro MATSUURA
This paper represents a cycle-based logic simulation method using an LUT cascade emulator, where an LUT cascade consists of multiple-output LUTs (cells) connected in series. The LUT cascade emulator is an architecture that emulates LUT cascades. It has a control part, a memory for logic, and registers. It connects the memory to registers through a programmable interconnection circuit, and evaluates the given circuit stored in the memory. The LUT cascade emulator runs on an ordinary PC. This paper also compares the method with a Levelized Compiled Code (LCC) simulator and a simulator using a Quasi-Reduced Multi-valued Decision Diagram (QRMDD). Our simulator is 3.5 to 10.6 times faster than the LCC, and 1.1 to 3.9 times faster than the one using a QRMDD. The simulation setup time is 2.0 to 9.8 times shorter than the LCC. The necessary amount of memory is 1/1.8 to 1/5.5 of the one using a QRMDD.
Itaru NAKAGAWA Ryo ISHIKAWA Kazuhiko HONJO Masao SHIMADA
An InGaP/GaAs HBT MMIC amplifier with an active balun has been developed for ultra-wideband radio systems (UWB). The MMIC was designed to drive a self-complementary antenna with a balanced mode, where an input impedance is 60π ohms. The MMIC consists of a common mode negative feed back ultra-wideband amplifier circuit, an active balun circuit, and a high impedance drive circuit. The developed amplifier provides a 3-dB gain roll-off bandwidth from 2.4 GHz to 10.8 GHz with a 14.1-dB linear power gain, and a linear power output up to 3 dBm. The developed amplifier with the active balun provides a 3-dB gain roll-off bandwidth from 2.3 GHz to 8.6 GHz with a 21.3-dB power gain in a balanced mode, and a linear power output up to 0.6 dBm. The measured total group delay is less than 32 psec. Output signals at the balanced output terminals of the MMIC were kept inverted with a steep pulse shape for an impulse input signal of 57-psec pulse width.
Hongwei ZHU Ilie I. LUICAN Florin BALASA
In real-time multimedia processing systems a very large part of the power consumption is due to the data storage and data transfer. Moreover, the area cost is often largely dominated by the memory modules. In deriving an optimized (for area and/or power) memory architecture, memory size computation is an important step in the exploration of the possible algorithmic specifications of multimedia applications. This paper presents a novel non-scalar approach for computing exactly the memory size in real-time multimedia algorithms. This methodology uses both algebraic techniques specific to the data-flow analysis used in modern compilers and, also, more recent advances in the theory of polyhedra. In contrast with all the previous works which are only estimation methods, this approach performs exact memory computations even for applications significantly large in terms of the code size, number of scalars, and number of array references.
Mallik TATIPAMULA Ichiro INOUE Zafar ALI Hisashi KOJIMA Kohei SHIOMOTO Shigeo URUSHIDANI Shoichiro ASANO
The rapidly increasing bandwidth requirements of IP traffic mean that networks based on optical technologies in conjunction with IP routing technologies will provide the backbone of the next generation Internet. One of the major issues is how to construct an optical-technology-based backbone network that offers the economical transport of large-scale IP/MPLS services while achieving reliable, robust network. The key to achieving this objective lies in multilayer coordination technologies using Multi-Layer Service Network [MLSN] Architecture, that we previously proposed [2]. One of the important aspects of MLSN architecture is ability to effectively use GMPLS network resources by IP/MPLS service networks. We propose extensions to previously proposed MLSN architecture. The proposed extensions to MLSN architecture are tailored to address "service virtualization and separation" of various service networks over GMPLS backbone. As a part of this extended MLSN architecture, we introduce novel concepts known as Logical Router (LR) and Virtual Router (VR) that would enable border router to be services domain router, so that it can connect multiple service networks such as L2VPN, L3VPN etc., over GMPLS backbone by offering service separation or virtualization. This service separation/isolation greatly enhances the reliability of next generation networks, as any failure on one service should be isolated from others. We evaluate our extended network architecture against requirements for the large scale network targeting at introducing such new technology to cope with vast traffic explosion and challenges in operation and service provision sophistication.
Jonghun BAEK Ik-Jin JANG Byoung-Ju YUN
As a result of the growth of sensor-enabled mobile devices, in recent years, users can utilize diverse digital contents everywhere and anytime. However, the interfaces of mobile applications are often unnatural due to limited computational capability, miniaturized input/output controls, and so on. To complement the poor user interface (UI) and fully utilize mobility as feature of mobile devices, we explore possibilities for a new UI of mobile devices. This paper describes the method for recognizing and analyzing a user's continuous action including the user's various gestures and postures. The application example we created is mobile game called AM-Fishing game on mobile devices that employ the accelerometer as the main interaction modality. The demonstration shows the evaluation for the system usability.
Mitsuru TOMONO Masaki NAKANISHI Shigeru YAMASHITA Kazuo NAKAJIMA Katsumasa WATANABE
In a partially reconfigurable FPGA of the future, arbitrary portions of its logic resources and interconnection networks will be reconfigured without affecting the other parts. Multiple tasks will be mapped and executed concurrently in such an FPGA. Efficient execution of the tasks using the limited resources of the FPGA will necessitate effective resource management. A number of online FPGA placement methods have recently been proposed for such an FPGA. However, they cannot handle I/O communications of the tasks. Taking such I/O communications into consideration, we introduce a new approach to online FPGA placement. We present an algorithm for placing each arriving task in an empty area so as to complete all the tasks efficiently. We develop two fitting strategies to effectively handle I/O communications of the tasks. Our experimental results show that properly weighted combinations of these and two other previously proposed strategies enable this algorithm to run very fast and make an effective placement of the tasks. In fact, we show that the overhead associated with the use of this algorithm is negligible as compared to the total execution time of the tasks.
Tokio KANEDA Atsushi SANADA Hiroshi KUBO
A novel two-dimensional (2D) beam scanning antenna array using composite right/left-handed (CRLH) leaky-wave antennas (LWAs) is proposed. The antenna array consists of a set of CRLH LWAs and a Butler matrix (BM) feeding network. The direction of the beam can be scanned two-dimensionally in one plane by changing frequency and in the other plane by switching the input ports of the BM. A four-element antenna array in the microstrip line configuration operating at 10.5 GHz is designed with the assistance of full-wave simulations based on the method of moment (MoM) and the finite-element method (FEM). The antenna array is fabricated and radiation characteristics are measured. The wide range 2D beam scanning operation with the angle from -30 deg to +25 deg in one plane by sweeping frequency from 10.25 GHz to 10.7 GHz and with four discrete angles of -46 deg, -15 deg, +10 deg, and +35 deg in the other plane by switching the input port is achieved.
Roberto ROJAS-CESSA Zhen GUO Nirwan ANSARI
Combined input-crosspoint buffered (CICB) packet switches have been of research interest in the last few years because of their high performance. These switches provide higher performance than input-buffered (IB) packet switches while requiring the crosspoint buffers run at the same speed as that of the input buffers in IB switches. Recently, it has been shown that CICB switches with one-cell crosspoint buffers, virtual output queues, and simple input and output arbitrations, provide 100% throughput under uniform traffic. However, it is of general interest to know the maximum throughput that a CICB switch, with no speedup, can provide under admissible traffic. This paper analyzes the throughput performance of a CICB switch beyond uniform traffic patterns and shows that a CICB switch with one-cell crosspoint buffers can provide 100% throughput under admissible traffic while using no speedup.
Jiahong WANG Takuya FUKASAWA Shintaro URABE Toyoo TAKATA Masatoshi MIYAZAKI
Data mining across different companies, organizations, online shops, or the likes is necessary so as to discover valuable shared patterns, associations, trends, or dependencies in their shared data. Privacy, however, is a concern. In many situations it is required that data mining should be conducted without any privacy being violated. In response to this requirement, in this paper we propose an effective distributed privacy-preserving data mining approach called SDDM. SDDM is characterized by its ability to resist collusion. Unless the number of colluding sites in a distributed system is larger than or equal to 4, privacy cannot be violated. Results of performance study demonstrated the effectiveness of SDDM.
Jia HOU Moon Ho LEE Kwangjae LEE
In this letter, we define the generalized doubly stochastic processing via Jacket matrices of order-2n and 2n with the integer, n≥2. Different from the Hadamard factorization scheme, we propose a more general case to obtain a set of doubly stochastic matrices according to decomposition of the fundaments of Jacket matrices. From order-2n and order-2n Jacket matrices, we always have the orthostochastoc case, which is the same as that of the Hadamard matrices, if the eigenvalue λ1 = 1, the other ones are zeros. In the case of doubly stochastic, the eigenvalues should lead to nonnegative elements in the probability matrix. The results can be applied to stochastic signal processing, pattern analysis and orthogonal designs.