EPCglobal architecture framework is divided into identify, capture, and share layers and defines a collection of standards. It is not fully adequate to build IoT applications because the transducer capability is lacking. IEEE 1451 is a set of standards that defines data exchange format, communication protocols, and various connection interfaces between sensors/actuators and transducer interface modules. By appending IEEE 1451 transducer capability to EPCglobal architecture framework, a consistent EPC scheme expression for heterogeneous things can be achieved at identify layer. It is benefit to extend the upper layers of EPCglobal architecture framework seamlessly. In this paper, we put our emphasis on how to leverage the transducer capability at the capture layer. A device cycle, transducer cycle specification, and transducer cycle report are introduced to collect and process sensor/actuator data. The design and implementation of GS1 EPCglobal Application Level Events (ALE) modules extension are proposed for explaining the design philosophy and verifying the feasibility. It will interact with the capture and query services of EPC Information Services (EPCIS) for IoT applications at the share layer. By cooperating and interacting with these layers of EPCglobal architecture framework, the IoT architecture EPCglobal+ based on international standards is built.

Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.

The visual inspection of defects in products is heavily dependent on human experience and instinct. In this situation, it is difficult to reduce the production costs and to shorten the inspection time and hence the total process time. Consequently people involved in this area desire an automatic inspection system. In this paper, we propose a hardware neural network, which is expected to provide high-speed operation for automatic inspection of products. Since neural networks can learn, this is a suitable method for self-adjustment of criteria for classification. To achieve high-speed operation, we use parallel and pipelining techniques. Furthermore, we use a piecewise linear function instead of a conventional activation function in order to save hardware resources. Consequently, our proposed hardware neural network achieved 6GCPS and 2GCUPS, which in our test sample proved to be sufficiently fast.

To apply network monitoring functions to emerging high-quality video streaming services, we proposed an application-coexistent monitor (APCM). In APCM, a streaming server can works as an active monitor and a passive monitor. In addition, IP packets sent from the server carry monitoring information together with application's data such as video signals. To achieve APCM on a 10-Gbps network, we developed a network interface card for an application-coexistent wire-rate network monitor (AWING NIC). It provides (1) a function to append GPS-based accurate timestamps to every packet that streaming applications send and receive, which can be used for real-time monitoring of delays and inter-packet gap, and (2) functions to capture and generate 10-Gbps wire-rate traffic without depending on packets' size, achieved by our highly-efficient DMA-transfer mechanisms. Such monitoring capability are unprecedented in existing PC-based systems because of the limitation in PC system's architecture. As an evaluation of APCM in an actual network, we conducted an experiment to transmit a 6-Gbps high-quality video stream over an IP network with the system in which we installed the AWING NIC. The results revealed that the video stream became highly bursty by passing through the network, and the observed smallest inter-packet gap corresponds to the value of 10-Gbps wire-rate traffic, which supports the effectiveness of our development.

We have developed an OC-48c (2.4 Gbps) PCI-compliant network interface card and drivers with the aim of evaluating the effectiveness of our proposed link layer protocol MAPOS. In this paper, we study the effectiveness of MAPOS particularly from the viewpoint of the influence of packet sizes up to the 64-kbyte jumbo MTU size and the effectiveness of our new implementation of the non-interrupt-driven sending process and interrupt batching receiving process deployed to improve the throughput in short-packet transmissions. Our main findings are as follows; Enlarging the packet size up to 64-kbyte MTU improves the performance in transmission. OC-48c wire speed is achieved with packet sizes larger than 16 kbytes. Implementation of the non-interrupt-driven sending process and the interrupt batching receiving process improves the performance of short-packet transmission. In particular, the transmission throughput is improved by 50% when 64-byte short packets are used. The maximum loss-free receive rate is also raised by 50% when 4-kbyte packets arrive. With a high-performance CPU, the data-transfer speed of the DMA controller for jumbo packets cannot keep up with the packet-queueing speed of the CPU. Our proposed procedure for adaptive algorithm switching method can resolve this problem. The maximum TCP throughput observed in our measurement using the latest PCs and MAPOS OC-48c PCI card was 2342.5 Mbps. This throughput represents the highest performance in a legacy-PCI-based system according to the results database of the benchmarking software.

Various I/O interface technologies in today's PC platform are classified into four categories, (1) ASIC (memory Controller) from / to Main Memory, (2) MPU from /to ASIC (Memory Controller), (3) ASIC (Memory Controller) from / to ASIC (Graphic Controller) and (4) ASIC from / to Peripherals. As to Category 1, effectiveness of SSTL is shown in DIMM application of SDRAM and DDR SDRAM over 100 MHz frequency. Furthermore a comparison is made between SLDRAM and D- RDRAM from the technology point of view. Concerning Categories 2 through 4, several interfaces such as PCI, AGP, GTL, HSTL and LVDS are reviewed. Interface technologies will keep playing an important role since computer systems require higher and higher speeds.