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[Keyword] PGS(2hit)

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  • A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications

    Zheng SUN  Dingxin XU  Hongye HUANG  Zheng LI  Hanli LIU  Bangan LIU  Jian PANG  Teruki SOMEYA  Atsushi SHIRANE  Kenichi OKADA  

     
    PAPER-Electronic Circuits

      Pubricized:
    2020/04/15
      Vol:
    E103-C No:10
      Page(s):
    505-513

    This paper presents a miniaturized transformer-based ultra-low-power (ULP) LC-VCO with embedded supply pushing reduction techniques for IoT applications in 65-nm CMOS process. To reduce the on-chip area, a compact transformer patterned ground shield (PGS) is implemented. The transistors with switchable capacitor banks and associated components are placed underneath the transformer, which further shrinking the on-chip area. To lower the power consumption of VCO, a gm-stacked LC-VCO using the transformer embedded with PGS is proposed. The transformer is designed to provide large inductance to obtain a robust start-up within limited power consumption. Avoiding implementing an off/on-chip Low-dropout regulator (LDO) which requires additional voltage headroom, a low-power supply pushing reduction feedback loop is integrated to mitigate the current variation and thus the oscillation amplitude and frequency can be stabilized. The proposed ULP TF-based LC-VCO achieves phase noise of -114.8dBc/Hz at 1MHz frequency offset and 16kHz flicker corner with a 103µW power consumption at 2.6GHz oscillation frequency, which corresponds to a -193dBc/Hz VCO figure-of-merit (FoM) and only occupies 0.12mm2 on-chip area. The supply pushing is reduced to 2MHz/V resulting in a -50dBc spur, while 5MHz sinusoidal ripples with 50mVPP are added on the DC supply.

  • Noise Suppression Methods Using Spiral with PGS in PCB

    Tong-Ho CHUNG  Jong-Gwan YOOK  

     
    BRIEF PAPER-Electronic Circuits

      Vol:
    E96-C No:5
      Page(s):
    752-754

    In this paper, several spiral inductors with various ground clearance structures and turns were investigated to achieve noise suppression up to the fourth harmonic (3.2 GHz) regime of DDR3-1600. Their performances were characterized in terms of their capability to effectively suppress simultaneous switching noise (SSN) in the frequency region of interest. For a wider noise suppression bandwidth, a spiral inductor with large ground clearance, which provides a high self resonance frequency (SRF) as well as high inductances, was implemented. The proposed spiral inductor exhibited good noise suppression characteristics in the frequency domain and achieved 50% voltage fluctuation reduction in the time domain, compared to the identical 4-turn spiral without pattern ground structure.