We developed a method for analysis of boron penetration and gate depletion using N+ and P+ dual-gate PMOSFETs. An N+ gate PMOSFETs, which is immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P+ gate PMOSFETs fabricated using identical N- substrates. We showed the importance of Vth fluctuation analysis and found that the Vth fluctuation in N+ gate PMOSFETs was negligible, but, the Vth fluctuation in P+ gate PMOSFETs was significant, indicating that the Vth fluctuation in P+ gate PMOSFETs was dominated by boron penetration. It was also shown, for the first time, that boron penetration occurred with gate depletion, and gate depletion must be very strong to suppress boron penetration. The dual-gate PMOSFET method makes it possible to select high-performance G-bit DRAM fabrication processes that are robust against Vth fluctuation.

Surface-channel PMOSFETs are suitable for use in the quarter micron CMOS devices. For surface-channel PMOSFETs with p+ poly-Si gates, boron penetration and hot-carrier effects were investigated. When the annealing temperature is higher and the gate oxide is thinner, a larger threshold voltage shift was observed for p+ poly-Si PMOSFETs, because of boron penetration. Furthermore, PMOSFETs with BF2-implanted gates cause larger boron penetration than those with Boron-implanted gates. Howerer, the PMOSFET lifetime, determined by hot-carrier reliability, does not depend on the degree of boron penetration. Instead, it depends on doping species, that is, BF2 and Boron. PMOSFETs with BF2-implanted gates have about 100 times longer lifetime than those with Boron-implanted gates. The main reason for the longer lifetime of BF2-doped PMOSFETs is the incorporation of fluorine in the gate oxide of the PMOSFET with the BF2-implanted gate, resulting in the smaller electron trapping in the gate oxide. The maximun allowed supply voltage,based on the hot-carrier reliability, is higher than4V for sub-half micron PMOSFETs with BF2- or Boron-implanted poly Si gates.

Single-drain PMOSFET's with a very shallow source and drain were fabricated using a new doping method called rapid vapor-phase doping (RVD). This process is carried out in hydrogen atmosphere using B2H6 as a source gas. By varying flow rate of B2H6 and the doping time, shallow boron doped layers which are suitable for source and drain regions of MOSFET's are formed. The fabricated RVD-PMOSFET's have 50-nm source and drain regions with peak concentration of 41020 cm-3 which were formed under the condition of 800, B2H6 flow rate of 50 ml/min. The junction depth was one third of those formed by conventional low-energy BF2 ion implantation. RVD-PMOSFET's showed normal operation down to poly-Si gate length Lg of 0.18 µm. The advantage of shallow junction was clearly shown by the threshold voltage roll-off characteristics, that is, it was suppressed down to 0.18 µm, whereas in conventional device, roll-off occurred below 0.6 µm. This better short channel behavior suggests that RVD forms shallow source and drain regions with weaker lateral diffusion. This result confirms that RVD is an effective method for forming shallow junctions for MOSFET's.