In this paper, to make asynchronous circuit design easy, we propose a conversion method from synchronous Register Transfer Level (RTL) models to asynchronous RTL models with bundled-data implementation. The proposed method consists of the generation of an intermediate representation from a given synchronous RTL model and the generation of an asynchronous RTL model from the intermediate representation. This allows us to deal with different representation styles of synchronous RTL models. We use the eXtensible Markup Language (XML) as the intermediate representation. In addition to the asynchronous RTL model, the proposed method generates a simulation model when the target implementation is a Field Programmable Gate Array and a set of non-optimization constraints for the control circuit used in logic synthesis and layout synthesis. In the experiment, we demonstrate that the proposed method can convert synchronous RTL models specified manually and obtained by a high-level synthesis tool to asynchronous ones.

In this paper, we propose a hardware architecture of high-speed sorted QR decomposition for 44 MIMO wireless communication systems. QR decomposition (QRD) is commonly used in many MIMO detection algorithms. In particular, sorted QR decomposition (SQRD) is the advanced algorithm to improve MIMO detection performance. We design an SQRD hardware architecture by using a modified Gram-Schmidt algorithm with pipelining and recursive processing. In addition, we propose an extended architecture which can decompose an augmented channel matrix for MMSE MIMO detection. These architecture can be applied in high-throughput MIMO-OFDM system such as IEEE802.11n which supports data throughput of up to 600 Mbps. We implement the proposed SQRD architecture and the proposed MMSE-SQRD architecture with 179k and 334k gates in 90 nm CMOS technology. These proposed design can achieve a high performance of up to 40.8 and 50.0 million 44 SQRD operations per second with the maximum operating frequency of 245 and 300 MHz.

Conventional algorithms for the joint estimation of carrier frequency offset (CFO) and I/Q imbalance no longer work when the I/Q imbalance depends on the frequency. In order to correct the imbalance across many frequencies, the compensator needed is a filter as opposed to a simple gain and phase compensator. Although, algorithms for estimating the optimal coefficients of this filter exist, their complexity is too high for hardware implementation. In this paper we present a new low complexity algorithm for joint estimation of CFO and frequency dependent I/Q imbalance. For the first part, we derive the estimation scheme using the linear least squares algorithm and examine its floating point performance compared to conventional algorithms. We show that the proposed algorithm can completely eliminate BER floor caused by CFO and I/Q imbalance at a lesser complexity compared to conventional algorithms. For the second part, we examine the hardware complexity in fixed point hardware and latency of the proposed algorithm. Based on BER performance, the circuit needs a wordlength of at least 16 bits in order to properly estimate CFO and I/Q imbalance. In this configuration, the circuit is able to achieve a maximum speed of 115.9 MHz in a Virtex 5 FPGA.

This paper deals with our works on developing a high-throughput wireless LAN using a group layered space-time (GLST) system with low-complexity MIMO decoder. It achieves the throughput of 600 Mbps for 30 meter propagation distance by utilizing 80 MHz bandwidth in the 5 GHz frequency band. Run test under channel model B of IEEE802.11TGn demonstrates its excellent performance. The register transfer level results show that the developed system is synthesized successfully and the prototyping in the target FPGA chips of Stratix II EP2S180F1508C4 gives the expected results.

A complete system for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform is introduced. The novel power-efficient FPGA architecture was designed and simulated in STM 0.18 µm CMOS technology. The detailed design and circuit characteristics of the Configurable Logic Block, the interconnection network, the switch box and the connection box were determined and evaluated in terms of energy, delay and area. A number of circuit-level low-power techniques were employed because power consumption was the primary concern. Additionally, a complete tool framework for the implementation of digital logic circuits in FPGA platforms is introduced. Having as input VHDL description of an application, the framework derives the reconfiguration bitstream of FPGA. The framework consists of: i) non-modified academic tools, ii) modified academic tools and iii) new tools. Furthermore, the framework can support a variety of FPGA architectures. Qualitative and quantitative comparisons with existing academic and commercial architectures and tools are provided, yielding promising results.

We present a new approach to the power modeling of synthesizable soft macros, which uses the characteristics of individual input signals for high accuracy. We also present the parameterized power model, developed using the proposed approach, which can relieve us from the power characterization for all possible macro sizes. Extensive experiments illustrate that the proposed approaches exhibit the overall modeling errors below 4.24% and 4.71% for benchmark macros before and after parameterization, when compared with the results of gate-level analysis.