We propose a novel hierarchical transmission method of DCT coefficients using multi-code DS/SS modulation. For low resolution image transmission over noisy channel, an error resilient and graceful degradation technique is necessary. Here, the DCT coefficients are divided into each stratum (a branch of multi-code DS/SS) and transmitted simultaneously through a noisy channel. By assigning an appropriate transmission energy that corresponds to their source energy variances, energy assignment, it is possible to maintain picture quality effectively even in a noisy channel. Analysis of this method was performed using an image data model, 2-D Gauss-Markov random field, which showed that picture quality is maintained even in the noisy channel condition.

A reaction-diffusion computer is a large-scale array of elementary processors, micro-volumes of chemical medium, which act, change their states determined by chemical reactions, concurrently and interact locally, via local diffusion of chemical species; it transforms data to results, both represented by concentration profiles of chemical species, by traveling and colliding waves in spatially extended chemical media. We show that reaction-diffusion processors, simulated or experimental, can solve a variety of tasks, including computational geometry, robot navigation, logics and arithmetics.

Recently, a new light-weight version of the secure electronic transaction protocol was proposed. The protocol can achieve two goals. One goal is that the security level is the same as the SET protocol. The other goal is to reduce the computational time in message generation and verification, and reduce the communication overhead. However, the protocol has a weakness, which is that non-repudiation is acquired, but confidentiality is lost. In this paper, we point out the weakness of the protocol. We also propose an improvement to the protocol to overcome this weakness.

This paper presents a model-based study of SET (Single-Electron-Transistor) logic gate family for synthesizing binary, MV (Multiple-Valued) and mixed-mode logic circuits. The use of SETs combined with MOS transistors allows compact realization of basic logic functions that exhibit periodic transfer characteristics. The operation of basic SET logic gates is successfully confirmed through SPICE circuit simulation based on the physical device model of SETs. The proposed SET logic gates are useful for implementing binary logic circuits, MV logic circuits and binary-MV mixed-mode logic circuits in a highly flexible manner. As an example, this paper describes design of various parallel counters for carry-propagation-free arithmetic, where MV signals are effectively used to achieve higher functionality with lower hardware complexity.

Some conventional beamformers require the direction of the desired signal. The performance of such beamformers can substantially be degraded even in the presence of small error on the directional information. In this letter, we propose a prefilter-type beamforming scheme robust to directional error by employing a simple compensator. The performance of the proposed scheme is verified by computer simulation.

This report describes a concrete method for realizing adiabatic charging reversible logic. First, we investigate the stabilization properties of a charge recycle regenerator using a switched capacitor circuit by SPICE simulation and an analytical method. In the N-step case, we proved that a step waveform is spontaneously generated. Next, for combinational logic, we propose an adiabatic charging binary decision diagram logic gate (AC-BDD) that uses this regenerator. The AC-BDD uses pass transistor logic based on a BDD, which is suitable for adiabatic logic. 8-bit AC-BDD multipliers were fabricated, and it is clarified that power consumption is reduced to 15% that of the same-rule-designed CMOS at 1 V and 1 MHz. Finally, we propose clocked energy reversible logic (CERL) that maintains the CMOS architecture for CMOS compatibility. CERL can reduce the clocked energy, which is used for charging the clock load capacitance, to 10% that of CMOS by using a power clock from the charge recycle regenerator.

A new approach for ultra-low-power LSIs based on quantum devices is presented and its present status and critical issues are discussed with a brief background review on the semiconductor nanotechnology. It is a hexagonal binary decision diagram (BDD) quantum logic circuit approach suitable for realization of ultra-low-power logic/memory circuits to be used in new applications such as intelligent quantum (IQ) chips embedded in the ubiquitous network environment. The basic concept of the approach, circuit examples showing its feasibility, growth of high density nanostructure networks by molecular beam epitaxy (MBE) for future LSI implementation, and the key processing issues including the device isolation issue are addressed.

This paper provides a computational method to construct a Lyapunov function to prove a stability of hybrid automata that can have nonlinear vector fields. Algebraic inequalities and equations are formulated, which are solved via LMI optimization. Numerical examples are presented to illustrate the proposed method.

To fulfill the computing demands in visual media processing, we have been investigating a parallel processing system to improve the processing speed of the visual media related to applications from the point of view of a memory system within a single instruction multiple data (SIMD) computer. In this paper, we have introduced MAMS-PP4, which is similar to a pipelined SIMD architecture type and consists of pq processing elements (PEs) as well as a multi-access memory system (MAMS). MAMS supports simultaneous access to pq data elements within a horizontal (1 pq), a vertical (pq 1) or a block (p q) subarray with a constant interval in an arbitrary position in an M N array of data elements, where the number of memory modules, m, is a prime number greater than pq. MAMS reduces the memory access time for an SIMD computer and also improves the cost and complexity that involved in controlling the large volume of data demanded in visual media applications. PE is designed to be a two-state machine in order to utilize MAMS efficiently. MAMS-PP4 was fabricated into ASIC using TOSHIBA TC240C series library and a test board was used to measure the performance of ASIC. The test board consists of devices such as an MPC860 embedded-PCI board, two ASICs and a FPGA for the control units. Experiment was done on various computer systems in order to compare the performance of MAMS-PP4 using morphological operations as the application. MAMS-PP4 shows a respectful and consistent processing speed.

We introduce an inheritance concept into a specification method of a concurrent system in order to reuse and refine existing specifications. Reusability by inheritance is emphasized in this paper. We take multiple inheritance to enable to reuse several specifications at a time. An upper specification can be skillfully reused by dividing inherited parts and non-inherited ones if the specification contains unnecessary parts for a lower specification. As an application, we specify the FIPA contract net interaction protocol (IP) with the function of an agent authentication. This is accomplished by using multiple inheritance. We also specify the FIPA iterated contract net IP by reusing the FIPA contract net IP. We have been developing a validation support tool for specifications described with the proposed method.

An efficient VLSI architecture for 1-D lifting DWT is proposed in this paper. To achieve higherhardware utilization and higher throughput, the computations of all resolution levels are folded to both the same high-pass and low-pass filters. Besides, the number of registers in the folded architecture is minimized by using the generalized lifetime analysis. Owing to its regular and flexible structure, the design can be extended easily into different resolution levels, and its area is independent of the length of the 1-D input sequence. Compared with other known architectures, our design requires the least computing time for 1-D lifting DWT.

A high accuracy numerical technique based on the Finite Difference Time Domain (FDTD) method for a long dipole antenna analysis is presented. An improvement of the accuracy can be achieved without reducing the cell size by incorporating a quasi-static field behavior into the FDTD update equations. A closed form of the quasi-static field is obtained from a low frequency limit of a sinusoidal current distribution. The validity of the proposed algorithm is confirmed even when the length of dipole antenna is longer than half wavelength by comparing the results with the Method of Moment.

This paper is concerned with the signal processing aspects of the recently proposed interleave-division multiple-access (IDMA) scheme. We propose several low-cost detection algorithms to solve the problems of multiple-access, cross-antenna and intersymbol interference (ISI). The complexities (per user) of these algorithms are very low and increase either linearly or quadratically with the number of paths. It is shown that an IDMA system with a rate- 16-state convolutional code and a length-8 spreading sequence can support more than 100 users in a multipath fading channel with two receive antennas. This clearly indicates the great potential of IDMA systems.

Our goal is to realize an extra-large stereoscopic display in the open air for use by the general public. We have developed a stereoscopic large display by use of a full-color LED panel. Although the developed display enables viewers to view the stereoscopic images without any special glasses, it is necessary for the viewers to move to stand within the viewing areas. Movements of the viewers are considered to depend on arrangements of viewing areas. The purpose of this paper is to investigate the movements of viewers who watch different designs of stereoscopic LED displays with a parallax barrier, including conventional designs to provide multiple perspective images and designs to eliminate pseudoscopic viewing areas, and evaluate the performance of different viewing areas based on the obtained paths of the viewers. We have developed a real-time measurement system of a viewer's position by use of a camera on the ceiling. We have recorded the viewing movements caused by the shift of viewing areas. It was found that the viewers moved to stand on orthoscopic viewing positions. The movements of viewers who move to find a viewing area have been recorded with different designs of stereoscopic LED displays that provide different viewing areas. We have calculated the lateral moving time of the viewers'movements. It is shown that the elimination of pseudoscopic viewing areas reduces the lateral moving time. Thus, the real-time measurement system of a viewer's position has been utilized for evaluation of performance of the different designs of stereoscopic LED displays.

The effect of feedback delay and channel estimation error on closed-loop transmit diversity (CTD) systems is investigated in time-selective Rayleigh fading channels. Based on a minimum mean square error (MMSE) channel estimator, the variance of the estimation error is formulated in terms of fading index and the number of transmit antennas. A bit error rate (BER) expression for the CTD system is analytically derived as a function of channel estimation error, feedback delay, and fading index. It is shown that the BER performance of the CTD system improves as the length of training symbols increases and/or the frame length decreases. In the CTD system, more accurate channel estimation scheme is required to achieve its full gain as the number of employed transmit antennas increases. It is also found that the CTD system is applicable to the slowly moving channel environments, such as pedestrians, but not for fast moving vehicles.

In this paper, we consider a blind channel estimation and equalization for single input multiple output (SIMO) channels. It is based on the one-step forward multichannel linear prediction error method. The derivation of the existing method is based on the noiseless assumption, however, we analyze the effects of additive noise at the output of the one-step forward multichannel linear prediction error filters. Moreover, we derive analytical results for the error in the blind channel estimation and equalization using linear prediction.

Direct digital frequency synthesizers (DDFS) provide fast frequency switching with high spectral purity and are widely used in modern spread spectrum wireless communication systems. ROM-based DDFS uses a ROM lookup table to store the amplitude of a sine wave. A large ROM table is required for high spectral purity. However, a larger ROM uses more area and consumes more power. Several ROM compression methods, including Sunderland technique based on simple trigonometric identities and quantization & error compensation techniques, have been reported. In this paper, we suggest several new techniques to reduce the ROM size. One new technique uses more number of hierarchical levels in ROM structures. Another technique uses simple interpolation techniques combined with hierarchical ROM structures. Experimental results show that the new proposed techniques can reduce the required ROM size up to 24%, when compared to that of a resent approach.

Voice over Internet protocol (VoIP) is to transfer voice packets over IP networks, while voice signal is processed by using digital signal processing technology before being transmitted. VoIP quality cannot be expected, because it is hard to predict the influence of delay, packet loss rate, packet error, etc. It is difficult to rebuild the voice wave form, if a large amount of voice packets are lost. This paper mainly studies on how to maintain a better voice quality over hybrid fiber/coaxial (HFC) networks, if it is inevitable to drop packets. We particularly consider the data over cable service interface specification (DOCSIS) version 1.1 with the unsolicited grant service with activity detection (UGS/AD) for VoIP services. We propose a smallest successive times first (SSTF) scheduling algorithm to schedule VoIP packets for cable modem termination system (CMTS), which can support fair transmission and long-term transmission continuity for VoIP connections. We analyze voice quality about continuity of the transmitted VoIP packets, consecutive clipping times, and VoIP packet drop rate for all connections. Performance measurement shows excellent results for the proposed algorithm by simulation experiments and objective evaluation.

This paper presents an asynchronous data transfer scheme using 2-color 2-phase dual-rail encoding based on a differential operation and its circuit realization. The proposed encoding enables seamless asynchronous data transfer without inserting a spacer, because each logic value is represented by two kinds of codewords with dual-rail, called "color" data. Since the difference x-x between components of a codeword (x,x) becomes constant in every valid state, the data-arrival state can be detected by calculating the difference x-x. From the viewpoint of circuit implementation, during the state transition, since the dual-rail x and x are defined so as to transit differentially, the compatibility with a comparator using a differential amplifier becomes high, which results in reduction of the cycle time. It is evaluated using HSPICE simulation with a 0.18 µm CMOS technology that communication speed using the proposed dual-rail encoding becomes 1.4 times faster than that using conventional dual-rail encoding.

A very long instruction word (VLIW) digital signal processor (DSP), called ODiN, which could execute six instructions in a single cycle simultaneously, is designed and fabricated using 0.25 µm 1-ploy 5-metal standard cell static CMOS process. The ODiN core delivers maximum 600 MIPS with 100 MHz system clock. In order to achieve high performance operation, the designed core includes compact register files, orthogonal instruction set, single cycle operations for most instructions, and parallel processing based on software scheduling. In addition, a Viterbi decoder processor and a FFT processor that are embedded make it possible to implement software defined radio (SDR) applications efficiently.