A 7GS/s complete-DDFS-solution featuring a two-times interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for random swapping thermometer coding dynamic element matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The proposed techniques enable a 7 GS/s operation with a spurious-free dynamic range better than 32dBc over the full Nyquist bandwidth. The worst case narrowband SFDR is 42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s·2(SFDR/6)/W. A proof-of-concept chip with an active area of only 0.22mm2 was measured in prototypes encapsulated in a 144-pins low profile quad flat package.

A new class of visible light communication (VLC) systems, namely image sensor (IS) based VLC systems, has emerged. An IS consists of a two-dimensional (2D) array of photodetectors (PDs), and then VLC systems with an IS receiver are capable of exploiting the spatial dimensions invoked for transmitting information. This paper aims for providing a brief survey of topics related to the IS-based VLC, and then provides a matrix representation of how to map a series of one dimensional (1D) symbols onto a set of 2D symbols for efficiently exploit the associate grade of freedom offered by 2D VLC systems. As an example, the matrix representation is applied to the symbol mapping of layered space-time coding (L-STC), which is presented to enlarge the coverage of IS-based VLC that is limited by pixel resolution of ISs.

Spatial modulation (SM) is introduced into layered space-time coding (L-STC) used in image sensor (IS)-based visible light communication (VLC) systems. STC was basically investigated for extending the communication range of the IS-based VLC link [10], although it is out of the range when IS receivers are at the long distance from the LED array of the transmitter where the number of pixels capturing the transmitter on the image plane is less than the number of LEDs of the array. Furthermore, L-STC was done in [11] for increasing the reception rate with improving the pixel resolution while the receiver was approaching the transmitter. In this paper, SM is combined into L-STC by mapping additional information bits on the location of the pair of STC bit matrices of each layer. Experimental results show that additional SM bits are extracted with no error, without deteriorating the reception quality of and shrinking the transmission range of the original L-STC.

Postcopy live migration is a promising alternative of virtual machine (VM) migration, which transfers memory pages after switching the execution host of a VM. It allows a shorter and more deterministic migration time than precopy migration. There is, however, a possibility that postcopy migration would degrade VM performance just after switching the execution host. In this paper, we propose a performance improvement technique of postcopy migration, extending the para-virtualized page fault mechanism of a virtual machine monitor. When the guest operating system accesses a not-yet-transferred memory page, our proposed mechanism allows the guest kernel to defer the execution of the current process until the page data is transferred. In parallel with the page transfer, the guest kernel can yield VCPU to other active processes. We implemented the proposed technique in our postcopy migration mechanism for Qemu/KVM. Through experiments, we confirmed that our technique successfully alleviated performance degradation of postcopy migration for web server and database benchmarks.

We propose a 2Nr MIMO ARQ scheme that uses multi-strata space-time codes composed of two layers. The phase and transmit power of each layer are assigned adaptively at each transmission round to mitigate the inter-layer interference and improve the block error rate by retransmission. Simulation results show that the proposed scheme achieves better performance than the conventional schemes in terms of the throughput and the block error rate.

Among spatial diversity schemes, orthogonal space-time block code (OSTBC) and cyclic delay diversity (CDD) have been widely studied for the cooperative wireless relaying system. However, conventional OSTBC and CDD cannot cope with change in the number of relays owing to low throughput or error performance. In this letter, we propose the space-time cyclic delay diversity (STCDD) scheme which provides good error performance and full rate. Simulation results show that bit error rate (BER) performance of the proposed STCDD is superior to that of OSTBC and CDD when sufficient quality of source-relay channels are guaranteed.

Properties of Kripke structures can be expressed by formulas of the modal µ-calculus. Despite its strong expressive power, the validity problem of the modal µ-calculus is decidable, and so are some of its variants enriched by inverse programs, graded modalities, and nominals. In this study, we show that the pre- and post-conditions of transformations of Kripke structures, such as addition/deletion of states and edges, can be expressed using variants of the modal µ-calculus. Combined with decision procedures we have developed for those variants, the properties of sequences of transformations on Kripke structures can be deduced. We show that these techniques can be used to verify the properties of pointer-manipulating programs.

In order for the interconnect effects due to process-induced variations to be applied to the designs in 0.13 µm and below, it is necessary to determine and characterize the realistic interconnect worstcase models with high accuracy and speed. This paper proposes new statistically-based approaches to the characterization of realistic interconnect worstcase models which take into account process-induced variations. The Effective Common Geometry (ECG) and Accumulated Maximum Probability (AMP) algorithms have been developed and implemented into the new statistical interconnect worstcase design environment. To verify this statistical interconnect worstcase design environment, the 31-stage ring oscillators are fabricated and measured with UMC 0.13 µm Logic process. The 15-stage ring oscillators are fabricated and measured with 0.18 µm standard CMOS process for investigating its flexibility in other technologies. The results show that the relative errors of the new method are less than 1.00%, which is two times more accurate than the conventional worstcase method. Furthermore, the new interconnect worstcase design environment improves optimization speed by 29.61-32.01% compared to that of the conventional worstcase optimization. The new statistical interconnect worstcase design environment accurately predicts the worstcase and bestcase corners of non-normal distribution where conventional methods cannot do well.

Various space time code (STC) designs have been proposed to obtain full diversity at full rate in multiple-input multiple-output (MIMO) channels for uncoded systems. However, commercial wireless systems typically employ powerful channel codes such as turbo codes and low density parity check (LDPC) codes together with an STC. For these applications, an STC optimized for uncoded systems may not provide the best performance. In this paper, an STC with relatively good performance over a wide range of code rates is proposed. Simulation results show that the performance of the proposed robust STC is very close to the best performance of the SM and the Golden code in various code rates.

AOC-SS (Advanced Orthogonal Code Spread Spectrum) modulation [1] is a flexible scheme that offers multi-rate transmission but causes a PAPR (Peak-to-Average Power Ratio) increase in proportion to the number of AOCs. Our solution to this problem is a new mapping technique. In addition, by combining with STC (Space-Time Coding), AOC-SS can resist multi-path fading. Computer simulations validate the proposed scheme.

Space-time coding (STC) schemes for communication systems employing multiple transmit and receive antennas have received considerable interest recently. On space-time coding, some algorithms with perfect channel state information (CSI) have been proposed. In certain fast varying situation, however, it may be difficult to estimate the channel accurately and it is natural to study the blind detection algorithm without CSI. In this paper, based on subspace, a new blind detection algorithm without CSI is proposed. Using singular value decomposition (SVD) on output signal, noise subspace and signal subspace, which keep orthogonal to each other, are obtained. By searching the intersection of the signal subspace and the limited symbol vector set, symbol detection is achieved. The simulations illustrate that the proposed algorithm significantly improves system performance by receiving more output signals relative to transmit symbols. Furthermore, the presented algorithm is robust to the fading channel that changes between two successive blocks.

This paper proposes a design method of STC for discrete unstructured systems based on D-L networks. The proposed scheme determines the control input composed of arbitrary system matrices of constructed D-L networks, and thus it makes it possible to design the STC for unstructured systems whose priori knowledges are not available. The simulation results show that the proposed scheme provides satisfactory performances both in MPS and NMPS for the STC design of unstructured systems.

Pb(ZrxTi1-x)O3 (PZT) thin films were prepared on various electrodes. When Ir system materials were used as electrodes, fatigue properties of PZT thin films were improved. Moreover, in the case of the PZT thin film on an Ir/IrO2 electrode, not only fatigue but imprint properties were clearly improved. We could find these improvements were caused by good barrier effect of IrO2 from secondary ion mass spectroscopy (SIMS) analysis. By applying these Ir system electrodes, we fabricated stacked capacitors on polycrystalline silicon (poly-Si) plugs. In spite of high temperature thermal processing, we found poly-Si plugs were ohmically connected with the bottom electrodes of the capacitors from hysteresis measurements and I-V characteristics, and could greatly expect them for practical use.

The Double-Sided Rugged poly Si (DSR) technology has been developed for high density DRAMs. The DSR technology was achieved using transformation of rugged poly Si caused by ion implantation. The DSR can increase the surface area of the storage electrode, because it has rugged surfaces on both upper and lower sides. The 2-FINs STC (STacked Capacitor cell) with DSR was fabricated in the cell size of 0.72 µm2, and it is confirmed that the DSR can increase the surface area 1.8 times larger than that of smooth poly Si. It is expected that 25 fF/bit is obtained with a 300 nm-thick storage electrode. These effects show that sufficient capacitance for 256 Mb DRAMs is obtained with a low storage electrode. It is confirmed that there is no degradation in C-V and I-V characteristics. Moreover, the DSR needs neither complicated process steps nor special technologies. Therefore, the DSR technology is one of the most suitable methods for 256 Mb DRAMs and beyond.