IEEE P802.3cg established a new pair of Ethernet physical layer devices (PHY), one of which, the short-reach 10BASE-T1S, uses 4B/5B mapping over Differential Manchester Encoding to maintain a data rate of 10 Mb/s at MAC/PLS interface, while providing in-band signaling between transmitter and receivers. However, 10BASE-T1S does not have any error correcting capability built into it. As a response to emerging building, industrial, and transportation requirements, this paper outlines research that leads to the possibility of establishing low-complexity, backward-compatible Forward Error Correction with per-frame configurable guaranteed burst error and erasure correcting capabilities over any 10BASE-T1S Ethernet network segment. The proposed technique combines a specialized, systematic Reed-Solomon code and a novel, three-tier, technique to avoid the appearance of certain inadmissible codeword symbols at the output of the encoder. In this way, the proposed technique enables error and erasure correction, while maintaining backwards compatibility with the current version of the standard.

In this study, the reference pure metal-oxide semiconductor field-effect transistors (MOSFETs) and low-voltage (LV) and high-voltage (HV) MOSFETs with a super-junction (SJ) structure in the drain side were experimentally compared. The results show that the drain-side engineering of SJs exerts negative effects on the electrostatic discharge (ESD) and latch-up (LU) immunities of LV n-channel MOSFETs, whereas for LV p-channel MOSFETs and HV n-channel laterally diffused MOSFETs (nLDMOSs), the effects are positive. Compared with the pure MOSFET, electrostatic discharge (ESD) robustness (It2) decreased by approximately 30.25% for the LV nMOS-SJ, whereas It2 increased by approximately 2.42% and 46.63% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively; furthermore, LU immunity (Vh) decreased by approximately 5.45% for the LV nMOS-SJ, whereas Vh increased by approximately 0.44% and 35.5% for the LV pMOS-SJ and HV nLDMOS-SJ, respectively. Thus, nMOS-SJ (pMOS-SJ and nLDMOS-SJ) has lower (higher) It2 and Vh, and this drain-side SJ structure of MOSFETs is an inferior (superior) choice for improving the ESD/LU reliability of LV nMOSs (LV pMOS and HV nLDMOS).

Improving robustness in electrostatic discharge (ESD) protection by inserting drain-side isolated silicon-controlled rectifiers (SCRs) in a high-voltage (HV) p-channel lateral-diffused MOSFET (pLDMOS) device was investigated in this paper. Additionally, the effects of anti-ESD reliability in the HV pLDMOS transistors provided by this technique were evaluated. From the experimental data, it was determined that the holding voltage (Vh) values of the pLDMOS with an embedded npn-arranged SCR and discrete thin-oxide (OD) layout on the cathode side increased as the parasitic SCR OD row number decreased. Moreover, the trigger voltage (Vt1) and the Vh values of the pLDMOS with a parasitic pnp-arranged SCR and discrete OD layout on the drain side fluctuated slightly as the SCR OD-row number decreased. Furthermore, the secondary breakdown current (It2) values (i.e., the equivalent ESD-reliability robustness) of all pLDMOS-SCR npn-arranged types increased (>408.4%) to a higher degree than those of the pure pLDMOS, except for npn-DIS_3 and npn-DIS_2, which had low areas of SCRs. All pLDMOS-SCR pnp-arranged types exhibited an increase of up to 2.2A-2.4A, except for the pnp_DIS_3 and pnp_DIS_2 samples; the pnp_DIS_91 increased by approximately 2000.9% (249.1%), exhibiting a higher increase than that of the reference pLDMOS (i.e., the corresponding pnp-stripe type). The ESD robustness of the pLDMOS-SCR pnp-arranged type and npn-arranged type with a discrete OD layout on the SCR cathode side was greater than that of the corresponding pLDMOS-SCR stripe type and a pure pLDMOS, particularly in the pLDMOS-SCR pnp-arranged type.

An 8-Mbit 0.18-µm CMOS 1T1C ferroelectric RAM (FeRAM) in a planar ferroelectric technology was developed. Even though the cell area of 2.48 µm2 is almost equal to that of a 4-Mbit stacked-capacitor FeRAM (STACK FeRAM) 2.32 µm2[1], the chip size of the developed 8-Mbit FeRAM, including extra 2-Mbit parities for the error correction code (ECC), is just 52.37 mm2, which is about 30% smaller than twice of the 4-Mbit STACK FeRAM device, 37.68mm2×2[1]. This excellent characteristic can be attributed to the large cell matrix architectures of the sectional cyclic word line (WL) that was used to increase the column numbers, and to the 1T1C bit-line GND level sensing (BGS)[2][3] circuit design intended to sense bit lines (BL) that have bit cells 1K long and a large capacitance. An access time of 52 ns and a cycle time of 77 ns in RT at a VDD of 1.8 V were achieved.

The purpose of our study is to develop an algorithm that would enable the automated detection of lacunar infarct on T1- and T2-weighted magnetic resonance (MR) images. Automated identification of the lacunar infarct regions is not only useful in assisting radiologists to detect lacunar infarcts as a computer-aided detection (CAD) system but is also beneficial in preventing the occurrence of cerebral apoplexy in high-risk patients. The lacunar infarct regions are classified into the following two types for detection: "isolated lacunar infarct regions" and "lacunar infarct regions adjacent to hyperintensive structures." The detection of isolated lacunar infarct regions was based on the multiple-phase binarization (MPB) method. Moreover, to detect lacunar infarct regions adjacent to hyperintensive structures, we used a morphological opening processing and a subtraction technique between images produced using two types of circular structuring elements. Thereafter, candidate regions were selected based on three features -- area, circularity, and gravity center. Two methods were applied to the detected candidates for eliminating false positives (FPs). The first method involved eliminating FPs that occurred along the periphery of the brain using the region-growing technique. The second method, the multi-circular regions difference method (MCRDM), was based on the comparison between the mean pixel values in a series of double circles on a T1-weighted image. A training dataset comprising 20 lacunar infarct cases was used to adjust the parameters. In addition, 673 MR images from 80 cases were used for testing the performance of our method; the sensitivity and specificity were 90.1% and 30.0% with 1.7 FPs per image, respectively. The results indicated that our CAD system for the automatic detection of lacunar infarct on MR images was effective.

A novel ratio-oriented definition based on 2T2R (Two transistors & two phase change resistors) phase change memory (PCM) cell structure is proposed to gain a high density by multilevel storage. In this novel solution, no reference is needed and good robustness remains still as conventional 2T2R, which is crucial when feature size scales to nanometer technology node. A behavioral SPICE model together with a preliminary simulation proves the idea to be feasible, and further optimization has been carried out. In addition, based on the ratio-oriented definition, a simpler and faster Error Control Coding (ECC) can be realized with n-Error-detection feasible.

We investigate the enhancement of the optical nonlinearity and the limit of the improvement of the response speed in CdSxSe1-x microcrystallites by measuring the effective optical nonlinear cross section (σeff), the energy decay time (T1) and the dephasing time in two kinds of semiconductor microcrystallites of CdS0.12Se0.8 microcrystallites embedded in alkaline multi-component glasses (CdSSeMs) and CdSe microcrystallites embedded in SiO2 thin film (CdSeMs). As the average radius of CdSSeMs decreases from 10 to 1 nm, the values of σeff and T1 gradually change from 2.610-16 to 1.110-16 cm2 and from dozens picoseconds to 4 psec, respectively. The size dependence of CdSSEMs shows that the energy level structure in the microcrystallite with a radius of less than a few nanometers is a two-level system, in which σeff is proportional to T2. The carrier recombination time (τ) of CdSSeMs with the average radius of 1 nm is estimated to 2 psec. As the average radius of a CdS0.12Se0.8 microcrystallite decreases from 9 to 3 nm, the values of T2 gradually change from 640 to 230 fsec at 18 K, respectively. The size and temperature dependences of T2 for the CdSSeMs show that there is the discrepancy between the theory and the measured T2. The discrepancy showes the presence of the acoustic-phonon-assisted relaxation processes other than the pure-dephasing processes. It is indicated that T2 becomes long by reducing the excessive acoustic-phonon-assisted relaxation processes, and that the longer T2 might enhance σeff. We investigate the enhancement of σeff in CdSeMs by making T2 longer. The τ, σeff, and T2 of CdSeM an average radius of 3 nm are 40 psec, 4.510-15 cm2, and 150 fsec at room temperature. The σeff is ten times as large as that of CdSSeM sample at the same average radius and the enhancement of σeff can be considered to be caused by the longer T2.