We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.

In this study we shall put forward a bidirectional synergetic neural network and investigate the crossassociation dynamics in an order parameter space. The present model is substantially based on a top-down formulation of the dynamic rule of an analog neural network in the analogy with the conventional bidirectional associative memory. It is proved that a complete association can be assured up to the same number of the embedded patterns as the number of neurons. In addition, a searching process of a couple of embedded patterns can be also realised by means of controlling attraction parameters as seen in the autoassociative synergetic models.

As a low-cost optical transceiver for access network systems, we propose a new monolithic transceiver photonic integrated circuit (PIC) fabricated by bandgap energy controlled selective metalorganic vapor phase epitaxy (MOVPE). In the PIC, all optical components are monolithically integrated. Thus, the number of optical alignment points is significantly reduced and the assembly costs of the module is decreased compared to those of hybrid modules, that use silica waveguides. Moreover, by using selective MOVPE, extremely low-loss buried heterostructure waveguides can be fabricated without any etching. In-plane bandgap energy control is also possible, allowing the formation of active and passive core layers simultaneously without complicated fabrication. The transceiver PIC showed fiber-coupled output power of more than 1 mW and receiver bandwidth of 7 GHz. Modulation and detection operations at 500 Mb/s were also demonstrated. As a cost effective fabrication technique for monolithic PICs, bandgap energy controlled selective MOVPE is a promising candidate.

The Bidirectional Reflectance Distribution Function (BRDF) is an intrinsic measurement of directional properties of the earth's surface. However, the estimation of the BRDF requires many remote sensing measurements of a given surface target from different viewing angles. In addition, a good atmospheric correction scheme is a prerequisite for such an attempt. The airborne POLDER sensor measures successively reflected radiation by terrestrial surfaces in a framed image form at different viewing angles during a single airplane pass, like taking snap-shot pictures. A specially improved atmospheric correction algorithm which is applicable to a framed image data by POLDER sensor is presented. The observed reflectance images taken successively by the airborne POLDER at slightly different viewing angles are converted to a series of surface albedo images by applying our atmospheric correction algorithm. Then, the BRDFs for three surface covers, namely, "River Water," "Forest," and "Rice Field," are estimated by using successive albedo images. It is found that the BRDF for "River Water" follows Lambert law at both 550nm and 850nm. It is also found that the BRDFs for "Forest" and "Rice Field" follow Lambert's law at 550nm, but they follow an anisotropic reflection law at 850nm and fitting parameters for their BRDFs are presented.

Recently, many researches on associative memories have been made a lot of neural network models have been proposed. Bidirectional Associative Memory (BAM) is one of them. The BAM uses Hebbian learning. However, unless the traning vectors are orthogonal, Hebbian learning does not guarantee the recall of all training pairs. Namely, the BAM which is trained by Hebbian learning suffers from low memory capacity. To improve the storage capacity of the BAM, Pseudo-Relaxation Learning Algorithm for BAM (PRLAB) has been proposed. However, PRLAB needs long learning epochs because of random initial weights. In this paper, we propose Quick Learning for BAM which greatly reduces learning epochs and guarantees the recall of all training pairs. In the proposed algorithm, the BAM is trained by Hebbian learning in the first stage and then trained by PRLAB. Owing to the use of Hebbian learning in the first stage, the weights are much closer to the solution space than the initial weights chosen randomly. As a result, the proposed algorithm can reduce the learning epocks. The features of the proposed algorithm are: 1) It requires much less learning epochs. 2) It guarantees the recall of all training pairs. 3) It is robust for noisy inputs. 4) The memory capacity is much larger than conventional BAM. In addition, we made clear several important chracteristics of the conventional and the proposed algorithms such as noise reduction characteristics, storage capacity and the finding of an index which relates to the noise reduction.

The Synchronous Optical Network (SONET) technology offers technical possibilities to build high speed transport networks and enables the operator to react quickly to the customers' capacity requirements. Furthermore the advanced SONET equipment, with standardized control and operation features, provides opportunities for new services, such as broadband services, and cost-effective ways to enhance existing services, such as network survivability improvement. But SONET technology can also create a certain degree of complexity in building cost-efficient network, especially in case of SONET Self-Healing Ring (SHR). It is a challenge for network planner to find an effective way to select the most economical SONET ring, or combination of rings, for given demands between a set of nodes that are supposed to be connected in a certain type of ring configuration. Three types of ring are standard today: path unidirectional, 2-fiber line protection bidirectional and 4-fiber line protection bidirectional. For a given network, the choosing of ring architecture based on economical considerations involves two major factors. They are capacity requirement and equipment cost. Capacity requirements of different SONET ring architectures depend upon different conditions. While facility line rate, which is a key factor in deciding what kind self-healing ring can be deployed economically on these requirements. Routing decisions play a key role in deciding the ring capacities required, especially for bidirectional rings. In the paper, we will make the economic study on how SONET SHR architecture works out with a variety of demand patterns, to find criteria for ring selection. We first present two efficient demand loading algorithms for BSHR capacity calculation, and then analyze the results from their application on a variety of demand patterns. The economic study for SONET SHR networks based on different architectures are also discussed.

An adder-based arithmetic VLSI processor using the SD number system is proposed for the applications of real-time computation such as intelligent robot system. Especially in the intelligent robot control system, not only high throughput but also small latency is a very important subject to make quick response for the sensor feedback situation, because the next input sample is obtained only after the robot actually moves. It is essential in the VLSI architecture for the intelligent robot system to make the latency as small as possible. The use of parallelism is an effective approach to reduce the latency. To meet the requirement, an architecture of a new multiple-valued arithmetic VLSI processor is developed. In the processor, addition and subtraction are performed by using the single adderbased processing element (PE). More complex basic arithmetic operations such as multiplication and division are performed by the appropriate data communications between the adder-based PEs with preserving their parallelism. In the proposed architecture, fine-grain parallel processing at the adder-based PE level is realized, and all the PEs can be fully utilized for any parallel arithmetic operations according to adder-based data dependency graph. As a result, the processing speed will be greatly increased in comparison with the conventional parallel processors having the different kinds of the arithmetic PEs such as an adder, a multiplier and a divider. To realize the arithmetic VLSI processor using the adder-based PEs, we introduce the signed-digit (SD) number system for the parallel arithmetic operations because the SD arithmetic has the advantage of modularity as well as parallelism. The multiple-valued bidirectional currentmode technology is also used for the implementation of the compact and high-speed adder-based PE, and the reduction of the number of the interconnections. It is demonstrated that these advantges of the multiple-valued technology are fully used for the implementation of the arithmetic VLSI processor. As a result, the latency of the proposed multiple-valued processor is reduced to 25% that of the binary processor integrated in the same chip size.

It is well known that the multiple-valued signed-digit (SD) arithmetic circuits have the attractive features of compactness and high-speed operation. However, both of these features have yet to be utilized fully. In this paper, we consider the application of a parallel-structure-based VLSI processor. A high-performance parallel-structure-based multiple-valued VLSI processor using the radix-2 SD number system is proposed. Its compactness makes the parallelism high under chip size limitations in comparison with the ordinary binary arithmetic circuits. Moreover, the speed of the single arithmetic module is very high in the SD arithmetic circuits, so that we can take advantage of the high-speed operation in the parallel-structure-based VLSI processor chip. The multiple-valued bidirectional current-mode technology is used not only in high-speed small sized arithmetic circuits, but also in reducing the number of connections in the parallel-structure-based VLSI processor. The proposed processor is specially developed for real-time digital control, where the performance is evaluated by delay time. Performance estimation using SPICE simulators shows that the delay time of proposed processor for matrix operations such as matrix multiplication is greatly reduced in comparison with a conventional binary processor.