This paper considers error-correction for information in array design, i.e., two-dimensional design such as QR-codes. The error model is multi deletion/substitution/erasure errors. Code construction for the errors and an application of the code are provided. The decoding technique uses an error-locator for deletion codes.

We propose two systematic constructions of deletion-correcting codes for protecting quantum inforomation. The first one works with qudits of any dimension l, which is referred to as l-adic, but only one deletion is corrected and the constructed codes are asymptotically bad. The second one corrects multiple deletions and can construct asymptotically good codes. The second one also allows conversion of stabilizer-based quantum codes to deletion-correcting codes, and entanglement assistance.

Maximum run-length limited codes are constraint codes used in communication and data storage systems. Insertion/deletion correcting codes correct insertion or deletion errors caused in transmitted sequences and are used for combating synchronization errors. This paper investigates the maximum run-length limited single insertion/deletion correcting (RLL-SIDC) codes. More precisely, we construct efficiently encodable and decodable RLL-SIDC codes. Moreover, we present its encoding and decoding algorithms and show the redundancy of the code.

This paper presents a successive cancellation (SC) decoding of polar codes modified for insertion/deletion/substitution (IDS) error channels, in which insertions and deletions are described by drift values. The recursive calculation of the original SC decoding is modified to include the drift values as stochastic variables. The computational complexity of the modified SC decoding is O (D3) with respect to the maximum drift value D, and O (N log N) with respect to the code length N. The symmetric capacity of polar bit channel is estimated by computer simulations, and frozen bits are determined according to the estimated symmetric capacity. Simulation results show that the decoded error rate of polar code with the modified SC list decoding is lower than that of existing IDS error correction codes, such as marker-based code and spatially-coupled code.

This paper constructs non-binary codes correcting a single b-burst of insertions or deletions with large cardinalities. This paper also provides insertion and deletion correcting algorithms of the constructed codes and evaluates a lower bound of the cardinalities of the constructed codes. Moreover, we evaluate a non-asymptotic upper bound on the cardinalities of arbitrary codes which correct a single b-burst of insertions or deletions.

In racetrack memories (RM), a position error (insertion or deletion error) results from unstable data reading. For position errors in RM with multiple read-heads (RHs), we propose a protograph-based LDPC coded system specified by a protograph and a protograph-aware permutation. The protograph-aware permutation facilitates the design and analysis of the coded system. By solving a multi-objective optimization problem, the coded system attains the properties of fast convergence decoding, a good decoding threshold, and a linear minimum distance growth. In addition, the coded system can adapt to varying numbers of RHs without any modification. The asymptotic decoding thresholds with a limited number of iterations verify the good properties of the system. Furthermore, for varying numbers of RHs, the simulation results with both small and large number of iterations, exhibit excellent decoding performances, both with short and long block lengths, and without error floors.

Racetrack memory (RM) has attracted much attention. In RM, insertion and deletion (ID) errors occur as a result of an unstable reading process and are called position errors. In this paper, we first define a probabilistic channel model of ID errors in RM with multiple read-heads (RHs). Then, we propose a joint iterative decoding algorithm for spatially coupled low-density parity-check (SC-LDPC) codes over such a channel. We investigate the asymptotic behaviors of SC-LDPC codes under the proposed decoding algorithm using density evolution (DE). With DE, we reveal the relationship between the number of RHs and achievable information rates, along with the iterative decoding thresholds. The results show that increasing the number of RHs provides higher decoding performances, although the proposed decoding algorithm requires each codeword bit to be read only once regardless of the number of RHs. Moreover, we show the performance improvement produced by adjusting the order of the SC-LDPC codeword bits in RM.

Codes over permutations and multipermutations have received considerable attention since the rank modulation scheme is presented for flash memories. Deletions in multipermutations often occur due to data synchronization errors. Based on the interleaving of several single-deletion-correcting multipermutation codes, we present a construction of multipermutation codes for correcting a burst of at most t deletions with shift magnitude one for t ≥2. The proposed construction is proved with including an efficient decoding method. A calculation example is provided to validate the construction and its decoding method.

In this letter, three types of constructions for multipermutation codes are investigated by using interleaving technique and single-deletion permutation codes to correct a predetermined number of adjacent deletions. The decoding methods for the proposed codes are provided in proofs and verified with examples. The rates of these multipermutation codes are also compared.

The development of an extremely efficient packet inspection algorithm for lookup engines is important in order to realize high throughput and to lower energy dissipation. In this paper, we propose a new lookup engine based on a combination of a mismatch detection circuit and a linked-list hash table. The engine has an automatic rule registration and deletion function; the results are that it is only necessary to input rules, and the various tables included in the circuits, such as the Mismatch Table, Index Table, and Rule Table, will be automatically configured using the embedded hardware. This function utilizes a match/mismatch assessment for normal packet inspection operations. An experimental chip was fabricated using 40-nm 8-metal CMOS process technology. The chip operates at a frequency of 100MHz under a power supply voltage of VDD =1.1V. A throughput of 100Mpacket/s (=51.2Gb/s) is obtained at an operating frequency of 100MHz, which is three times greater than the throughput of 33Mpacket/s obtained with a conventional lookup engine without a mismatch detection circuit. The measured energy dissipation was a 1.58pJ/b·Search.

This paper proposes an adaptive marker coding (AMC) for correction of insertion/deletion/substitution errors. Unlike the conventional marker codings which select marker-bit values deterministically, the AMC adaptively reverses the first and last bits of each marker as well as bits surrounding the marker. Decoding is based on a forward-backward algorithm which takes into account the dependency of bit-values around the marker. Evaluation shows that, for a channel with insertion/deletion error probability 1.8×10-2, the decoded BER of existing marker coding of rate 9/16 is 4.25×10-3, while that of the proposed coding with the same code rate is 1.73×10-3.

Turbo equalization is an iterative equalization and decoding technique that can achieve impressive performance gains for communication systems. In this letter, we investigate the turbo equalization method for the decoding of the Davey-MacKay (DM) construction over the IDS-AWGN channels, which indicates a cascaded insertion, deletion, substitution (IDS) channel and an additive white Gaussian noise (AWGN) channel. The inner decoder for the DM construction can be seen as an maximum a-posteriori (MAP) detector. It receives the beliefs generated by the outer LDPC decoder when turbo equalization is used. Two decoding schemes with different kinds of inner decoders, namely hard-input inner decoder and soft-input inner decoder, are investigated. Simulation results show that significant performance gains are obtained for both decoders with respect to the insertion/deletion probability at different SNR values.

Nonbinary M-ary data processed by data entry systems, such as keyboard devices and character recognition systems, often have various types of error, such as symbol-substitution errors, deletion errors, insertion errors, and adjacent-symbol-transposition errors. This paper proposes nonsystematic M-ary codes capable of correcting these errors. The code is defined as a set of codewords that satisfy three conditions required to correct substitution, deletion/insertion, and adjacent-symbol-transposition errors. Since symbol-substitution errors in data entry systems are usually asymmetric, this paper also presents asymmetric-symbol-substitution error correcting codes capable of correcting deletion, insertion, and adjacent-symbol-transposition errors. For asymmetric-symbol-substitution error correction, we employ a mapping derived from the vertex coloring in an error directionality graph. The evaluation shows that the asymmetric codes have three to five times larger number of codewords than the symmetric codes.

An Insertion-Deletion system, first introduced in [1], is a theoretical computing model in the DNA computing framework based on insertion and deletion operations. When insertion and deletion operations work together, as expected, they are very powerful. In fact, it has been shown that even the very restricted Insertion-Deletion systems can characterize the class of recursively enumerable languages [1]-[4]. In this paper, we investigate the computational power of Insertion-Deletion systems and show that they preserve the computational universality without using contexts.

We propose a method for reducing the size of a share in visual secret sharing schemes. The proposed method does not cause the leakage and the loss of the original image. The quality of the recovered image is almost same as that of previous schemes.

Before we gave a fast generalized minimum distance (GMD) decoding algorithm for one-point algebraic-geometry (AG) codes. In this paper, we propose another fast GMD decoding algorithm for these codes, where the present method includes an erasure deletion procedure while the past one uses an erasure addition procedure. Both methods find a minimal polynomial set of a given syndrome array, which is a candidate for an erasure-and-error locator polynomial set constrained with an erasure locator set of each size. Although both erasure addition and deletion GMD decoding algorithms have been established for one-dimensional algebraic codes such as RS codes, nothing but the erasure addition GMD decoding algorithm for multidimensional algebraic codes such as one-point AG codes have been given. The present erasure deletion GMD decoding algorithm is based on the Berlekamp-Massey-Sakata (BMS) algorithm from the standpoint of constrained multidimensional shift register synthesis. It is expected that both our past and present methods play a joint role in decoding for one-point AG codes up to the error correction bound.

This paper presents a class of binary block codes capable of correcting single synchronization errors and single reversal errors with fewer check bits than the existing codes by 3 bits. This also shows a decoding circuit and analyzes its complexity.

It is known that cycle slip due to frequency selective fading causes a burst error by symbol deletion or insertion, and has a serious effect on mobile radio communication systems. In this paper, first, we show that phase rotating modulation is suitable for code synchronization error detection. Next, we consider a code synchronization controller using correlation estimator of received sequence, and the controller combines the estimator with 2π/3-shifted modulation to construct a new code synchronization error control scheme as a cycle slip cancelling system. Furthermore, we apply the scheme to the multilevel trellis coded modulation (TCM). Finally, computer simulation results confirm that proposed scheme is capable of code synchronization error correction.

The maximum order complexity (MOC) of a sequence is a very natural generalization of the well-known linear complexity (LC) by allowing nonlinear feedback functions for the feedback shift register which generates a given sequence. It is expected that MOC is effective to reduce such an instability of LC as an extreme increase caused by the minimum changes of a periodic sequence, i. e. , one-symbol substitution, one-symbol insertion or one-symbol deletion per each period. In this paper we will give the bounds (lower and upper bounds) of MOC for the minimum changes of an m-sequence over GF(q) with period qn-1, which shows that MOC is much more natural than LC as a measure for the randomness of sequences in this case.

In this paper a new class of single error-correcting fixed block-length (d, k) codes has been proposed. The correctable error types are peak-shift error, insertion or deletion error, symmetric error, etc. The basic technique to construct codes is a systematic construction algorithm of multilevel sequences with a constant Lee weight (TALG algorithm). The coding rate and efficiency are considerably good, and hence the proposed new codes will be very useful for improving the reliability of high density magnetic recording.