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[Keyword] dual-rate(4hit)

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  • 82.5GS/s (8×10.3GHz Multi-Phase Clocks) Blind Over-Sampling Based Burst-Mode Clock and Data Recovery for 10G-EPON 10.3-Gb/s/1.25-Gb/s Dual-Rate Operation

    Naoki SUZUKI  Kenichi NAKURA  Takeshi SUEHIRO  Seiji KOZAKI  Junichi NAKAGAWA  Kuniaki MOTOSHIMA  

     
    PAPER

      Pubricized:
    2017/10/18
      Vol:
    E101-B No:4
      Page(s):
    987-994

    We present an 82.5GS/s over-sampling based burst-mode clock and data recovery (BM-CDR) IC chip-set comprising an 82.5GS/s over-sampling IC using 8×10.3GHz multi-phase clocks and a dual-rate data selector logic IC to realize the 10.3Gb/s and 1.25Gb/s dual-rate burst-mode fast-lock operation required for 10-Gigabit based fiber-to-the-x (FTTx) services supported by 10-Gigabit Ethernet passive optical network (10G-EPON) systems. As the key issue for designing the proposed 82.5GS/s BM-CDR, a fresh study of the optimum number of multi-phase clocks, which is equivalent to the sampling resolution, is undertaken, and details of the 10.3Gb/s cum 1.25/Gb/s dual-rate optimum phase data selection logic based on a blind phase decision algorithm, which can realize a full single-platform dual-rate BM-CDR, ate also presented. By using the power of the proposed 82.5GS/s over-sampling BM-CDR in cooperation with our dual-rate burst-mode optical receiver, we further demonstrated that a short dual-rate and burst-mode preamble of 256ns supporting receiver settling and CDR recovery times was successfully achieved, while obtaining high receiver sensitivities of -31.6dBm at 10.3Gb/s and -34.6dBm at 1.25Gb/s and a high pulse-width distortion tolerance of +/-0.53UI, which are superior to the 10G-EPON standard.

  • Ripple-Free Dual-Rate Control with Two-Degree-of-Freedom Integrator

    Takao SATO  Akira YANOU  Shiro MASUDA  

     
    PAPER-Systems and Control

      Vol:
    E101-A No:2
      Page(s):
    460-466

    A ripple-free dual-rate control system is designed for a single-input single-output dual-rate system, in which the sampling interval of a plant output is longer than the holding interval of a control input. The dual-rate system is converged to a multi-input single-output single-rate system using the lifting technique, and a control system is designed based on an error system using the steady-state variable. Because the proposed control law is designed so that the control input is constant in the steady state, the intersample output as well as the sampled output converges to the set-point without both steady-state error and intersample ripples when there is neither modeling nor disturbance. Furthermore, in the proposed method, a two-degree-of-freedom integral compensation is designed, and hence, the transient response is not deteriorated by the integral action because the integral action is canceled when there is neither modeling nor disturbance. Moreover, in the presence of the modeling error or disturbance, the integral compensation is revealed, and hence, the steady-state error is eliminated on both the intersample and sampled response.

  • Generalized Predictive Control in Fast-Rate Single-Rate and Dual-Rate Systems

    Takao SATO  Akira INOUE  

     
    LETTER-Systems and Control

      Vol:
    E90-A No:11
      Page(s):
    2616-2619

    This paper discusses design of Generalized Predictive Control (GPC) scheme. GPC is designed in two cases; the first is a dual-rate (DR) system, where the sampling interval of a plant output is an integer multiple of the holding interval of a control input, and the second is a fast-rate single-rate (FR-SR) system, where both the holding and sampling intervals are equal to the holding interval of the DR system. Furthermore, the relation between them is investigated, and this study gives the conditions that FR-SR and DR GPC become equivalent. To this end, a future reference trajectory of DR GPC is rewritten, and a future predictive output of the FR-SR GPC is rearranged.

  • GSIC Receiver with Adaptive MMSE Detection for Dual-Rate DS-CDMA System

    Seung Hee HAN  Jae Hong LEE  

     
    LETTER-Wireless Communication Technology

      Vol:
    E86-B No:9
      Page(s):
    2809-2814

    In this letter, we present groupwise successive interference cancellation (GSIC) receiver with adaptive minimum mean squared error (MMSE) detection and extended GSIC (EGSIC) receiver with adaptive MMSE detection for dual-rate DS-CDMA system. The receivers are GSIC receiver and EGSIC receiver combined with adaptive MMSE detection which is introduced to make initial bit detection more reliable. Furthermore, a multi-user detection scheme is introduced to mitigate the effect of multiple access interference (MAI) between users in a group which is usually ignored in conventional GSIC receiver and EGSIC receiver. Specifically, parallel interference cancellation (PIC) is adopted as a multi-user detection scheme within a group. It is shown that performance of the GSIC receiver and EGSIC receiver is significantly improved by employing adaptive MMSE detection. It is also shown that the performance of the receivers can be improved further by using PIC within a group.