In sixth-generation (6G) mobile communication system, it is expected that extreme high data rate communication with a peak data rate over 100Gbps should be provided by exploiting higher frequency bands in addition to millimeter-wave bands such as 28GHz. The higher frequency bands are assumed to be millimeter wave and terahertz wave where the extreme wider bandwidth is available compared with 5G, and hence 6G needs to promote research and development to exploit so-called terahertz wave targeting the frequency from 100GHz to 300GHz. In the terahertz wave, there are fundamental issues that rectilinearity and pathloss are higher than those in the 28GHz band. In order to solve these issues, it is very important to clarify channel characteristics of the terahertz wave and establish a channel model, to advance 6G radio access technologies suitable for the terahertz wave based on the channel model, and to develop radio-frequency device technologies for such higher frequency bands. This paper introduces a direction of studies on 6G radio access technologies to explore the higher frequency bands and technical issues on the device technologies, and then basic computer simulations in 100Gbps transmission using 100GHz band clarify a potential of extreme high data rate over 100Gbps.

In this paper, we introduce an LDPC decoder design for decoding a length-672 multi-rate code adopted in IEEE 802.15.3c standard. The proposed decoder features high performances in both data rate and power efficiency. A macro-layer level fully parallel layered decoding architecture is proposed to support the throughput requirement in the standard. For the proposed decoder, it takes only 4 clock cycles to process one decoding iteration. While parallelism increases, the chip routing congestion problem becomes more severe because a more complicated interconnection network is needed for message passing during the decoding process. This problem is nicely solved by our proposed efficient message permutation scheme utilizing exploited parity check matrix features. The proposed message permutation network features high compatibility and zero-logic-gate VLSI implementation, which contribute to the remarkable improvements in both area utilization ratio and total gate count. Meanwhile, frame-level pipeline decoding is applied in the design to shorten the critical path. To verify the above techniques, the proposed decoder is implemented on a chip fabricated using Fujitsu 65 nm 1P12L LVT CMOS process. The chip occupies a core area of 1.30 mm2 with area utilization ratio 86.3%. According to the measurement results, working at 1.2 V, 400 MHz and 10 iterations the proposed decoder delivers a 6.72 Gb/s data throughput and dissipates a power of 537.6 mW, resulting in an energy efficiency 8.0 pJ/bit/iteration. Moreover, a decoder of the same architecture but with no pipeline stage for low-profile application is also implemented and evaluated at post-layout level.

A wireless transceiver utilizing inductive coupling has been proposed for communication between chips in system in a package. This transceiver can achieve high-speed communication by using two-dimensional channel arrays. To increase the total bandwidth in the channel arrays, the density of the transceiver should be improved, which means that the inductor size should be scaled down. This paper discusses the scaling theory based on a constant magnetic field rule. By decreasing the chip thickness with the process scaling of 1/α, the inductor size can be scaled to 1/α and the data rate can be increased by α. As a result, the number of aggregated channels can be increased by α2 and the aggregated data bandwidth can be increased by α3. The scaling theory is verified by simulations and experiments in 350, 250, 180, and 90 nm CMOS.

High Rate Space-Time Block Codes (HR-STBCs) with greater than 1 symbol/transmission and simple decoding schemes are proposed. The HR-STBC demonstrates 3 dB Eb/No gain at BER = 10-3 compared with the conventional STBC when three transmit antennas and two receive antennas are utilized.

Channel estimation is one of the key technologies in mobile communications. Channel estimation is critical in providing high data rate services and to overcome fast fading in very high-speed mobile communications. This paper presents a novel channel estimation based on hybrid spreading of I and Q signals (CEHS). Simulation results show that it can effectively mitigate the influence of fast fading and enable to provide high data rates for very high speed mobile systems.