We have designed a new current-mode low-voltage, low-power, high-frequency CMOS VCO circuit. The main purpose of this new circuit is to obtain operational capabilities with more than 1 GHz oscillation frequency from one battery cell. The current-mode approach was adopted throughout the circuit design to achieve this. New differential-type delay cells in the current-mode operation enable extremely low supply voltage operation and superior linearity between the oscillation frequency and control voltage of a ring oscillator. A design which combines the transitions of each delay cell output enables the VCO's high-frequency operation. To obtain a sufficient current level at output, a current amplifier with a small amount of positive feedback is used. The unnecessary generation of spectral components caused by mismatched time delay of delay cells in a ring-oscillator, which is an inherent problem of the VCO in a ring-oscillator form, is 0also analyzed. The characteristics of the designed VCO were examined by the SPICE circuit simulation using standard CMOS 0.6µm devices. Operation with a 1 V power supply, 1 GHz oscillation frequency, and 5.7 mW power dissipation was verified.

A high-frequency approximate method for calculating the diffraction by a smooth convex surface is presented. The advantage of this method is the validity of it in the caustic region of the creeping rays where the Geometrical Theory of Diffraction (GTD) becomes invalid. The concept used in this method is based on the Method of Equivalent Edge Currents (EEC), and the equivalent line currents for creeping rays which are derived from the diffraction coefficients of the GTD are used. By evaluating the radiation integral of these equivalent line currents, the creeping ray contribution which is valid within the caustic region is obtained. In order to check the accuracy and the validity of the method, the diffraction problem by a perfectly conducting sphere of radius a is solved by applying the method, and the obtained results are compared with the exact and the GTD solutions. It is confirmed from the comparison that the failure of the GTD near the caustic is removed in this method and accurate solution is obtained in this area for high-frequency (ka8). Furthermore, it is also found that this method is valid in the backward region (0θ90, θ is an observation angle mesuered from an incident direction), whereas not in the forward region (90θ180).

A CMOS fully balanced current-mode filter is presented. A fully balanced current-mode integrator which is the basic building block is implemented by adding a very simple common-mode-rejection mechanism to fully differential one. The fully balanced operation can eliminate even order distortion, which is one of the drawbacks in previous continuous current-mode filter. Moreover, the additional circuit can work as not only common-mode-rejection mechanism but also Q-tuning circuit which compensates lossy elements due to finite output impedance of MOS FET. A prototype fifth-order low-pass lad-der filter designed in a standard digital 0.8µm CMOS process achieved a cut-off frequency (fC) of 100MHz; fC was tunable from 75MHz to 120MHz by varying a reference bias current from 50µA to 150µA. Using a single 3V power supply with a nominal reference current of 100µA, power dissipation per one pole is 30mW. The active filter area was 0.011mm2/pole and total harmonic distortion (THD) was 0.73 [%] at 80MHz, 80µA amplitude signal. Furthermore, by adjusting two bias currents, on chip automatic both frequency and Q controls are easily implemented by typical tuning systems, for example master-slave tuning systems [1].

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great dfficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.

A power converter with a new piezoelectric transformer is presented. The piezoelectric transformer, made of lead titanate solid solution ceramic, is operated with a thickness extensional vibration mode. This transformer can operate at high frequency, over several megahertz, with about 90% high efficiency. The resonant frequency for the transformer is 2 MHz. The power converter with the transformer applies the theory for a class-E switching converter using an electromagnetic transformer. Maximum output power was obtained when the switching frequency was slightly higher than the resonant frequency. 4.4 W output power was successfully obtained with 52% efficiency at 2.1 MHz switching frequency.