This paper presents a design of CMOS transimpedance amplifier (TIA) and peaking inductor for high speed, low power and small area. To realize high density integration of optical I/O, area reduction is an important figure as well as bandwidth, power and so on. To determine design parameters of multi-stage inverter-type TIA (INV-TIA) with peaking inductors, we derive a simplified model of the bandwidth and the energy per bit. Multi-layered on-chip inductors are designed for area-effective inductive peaking. A 5-stage INV-TIA with 3 peaking inductors is fabricated in a 65-nm CMOS. By using multi-layered inductors, 0.02 mm2 area is achieved. Measurement results show 45 Gb/s operation with 49 dBΩ transimpedance gain and 4.4 mW power consumption. The TIA achieves 98 fJ/bit energy efficiency.

This article presents the CMOS transimpedance amplifier (TIA) for gigabits optical communication, where an analytical method for designing a wideband TIA using different inductive peaking technology is introduced. In this study, we derive and analyze the transfer function (Vout/Iin) of the TIA circuit from the equivalent circuit model. By adding the peaking inductor in different locations, the TIA 3-dB bandwidth can be enhanced without sacrificing the transimpedance gain. These TIA designs have been realized by the advanced CMOS process, and the measured results confirm the predictions from the analytic approach, where the inductive peaking is an useful way to enhance the TIA bandwidth.