The reduction in the gate length of the current devices to 65 nm causes their I-V characteristics to depart from the traditional MOSFETs. As a result, manufacturing of new efficient devices in nanoscale is inevitable. The fundamental properties of the metallic and semi-conducting carbon Nanotubes (CNTs) make them alternatives to the conventional silicon-based devices. In this paper an ultra high-speed and energy-efficient full adder is proposed, using Carbon Nanotube Field Effect Transistor (CNFET) in nanoscale. Extensive simulation results using HSPICE are reported to show that the proposed adder consumes lower power, and is faster compared to the previous adders.

In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.

Carbon nanotubes (CNTs) offer unique properties such as highest current density exceeding 109 A/cm2, ultra-high thermal conductivity as high as that of diamond, ballistic transport along the tube and extremely high mechanical strength with high aspect ratio of more than 1000. Because of these remarkable properties, they have been expected for use as future wiring materials to solve several problems, for examples, stress and electro-migration, heat removal and fabrication of a small-sized via in future LSIs. In this paper, we demonstrate present status of CNT material technologies and the potential of metallic CNT vias. In particular, we report our original catalytic nano-particle technique for controlling the diameter and density of CNTs. We have succeeded in forming a 40-nm via with the CNT density of 91011/cm2, which is the highest density ever reported. The low temperature CVD growth and the electrical properties of CNT vias are also discussed.

With advent of the ubiquitous network era and due to recent progress of III-V nanotechnology, the present III-V heterostructure microelectronics will turn into what one might call III-V heterostructure nanoelectronics, and may open up a new future in much wider application areas than today, combining information technology, nanotechnology and biotechnology. Instead of the traditional top-down approach, new III-V heterostructure nanoelectronics will be formed on nanostructure networks formed by combination of top-down and bottom-up approaches. In addition to communication devices, emerging devices include high speed digital LSIs, various sensors, various smart-chips, quantum LSIs and quantum computation devices covering varieties of application areas. Ultra-low power quantum LSIs may become brains of smart chips and other nano-space systems. Achievements of new functions and higher performances and their on chip integration are key issues. Key processing issue remains to be understanding and control of nanostructure surfaces and interfaces in atomic scale.