Electrophysiology, which is the study of the electrical properties of biological tissues and cells, has become indispensable in modern clinical research, diagnostics, disease monitoring and therapeutics. In this paper we present a brief history of this discipline and how integrated circuit design shaped electrophysiology in the last few decades. We will discuss how biopotential amplifier design has evolved from the classical three-opamp architecture to more advanced high-performance circuits enabling long-term wearable monitoring of the autonomous and central nervous system. We will also discuss how these integrated circuits evolved to measure in-vivo neural circuits. This paper targets readers who are new to the domain of biopotential recording and want to get a brief historical overview and get up to speed on the main circuit design concepts for both wearable and in-vivo biopotential recording.

This paper presents a hippocampal cognitive prosthesis chip designed for restoring the ability to form new long-term memories due to hippocampal system damage. The system-on-chip (SOC) consists of a 16-channel micro-power low-noise amplifier (LNA), high-pass filters, analog-digital converters (ADCs), a 16-channel spike-sorter, a generalized Laguerre-Volterra model multi-input, multi-output (GLVM-MIMO) hippocampal processor, an 8-channel neural stimulator and peripheral circuits. The proposed LNA achieved a voltage gain of 50dB, input-referred noise of 3.95µVrms, and noise efficiency factor (NEF) of 3.45 with the power consumption of 3.3µW. High-pass filters with a 300-Hz bandwidth are used to filter out the unwanted local field potential (LFP). 4 12-bit successive approximation register (SAR) ADCs with a signal-to-noise-and-distortion ratio (SNDR) of 63.37dB are designed for the digitization of the neural signals. A 16-channel spike-sorter has been integrated in the chip enabling a detection accuracy of 98.3% and a classification accuracy of 93.4% with power consumption of 19µW/ch. The MIMO hippocampal model processor predict output spatio-temporal patterns in CA1 according to the recorded input spatio-temporal patterns in CA3. The neural stimulator performs bipolar, symmetrical charge-balanced stimulation with a maximum current of 310µA, triggered by the processor output. The chip has been fabricated in 40nm standard CMOS technology, occupying a silicon area of 3mm2.

To detect neural spike signals, low-power neural signal recording frontend circuits must amplify neural signals with below 100 µV amplitude and a few hundred Hz frequency while suppressing a large DC offset voltage, 1/f noise of MOSFETs, and induced noise of AC power supply. To overcome the problem of unwanted noise at such a low signal level, a low-noise neural signal detection amplifier with low-frequency noise suppression scheme was developed utilizing a new autozeroing technique. A test chip was designed and fabricated with a mixed signal 0.18-µm CMOS technology. The voltage gain of 39 dB at the bandwidth of the neural signal and the gain reduction of 20 dB at AC supply noise of 60 Hz were obtained. The input equivalent noise and power dissipation were 90 nV/root-Hz and 90 µW at a supply voltage of 1.5 V, respectively.