In conclusion, an initialization method has been introduced and studied to improve the SET speed in PCM. Before experiment verification, a two-dimensional finite analysis is used, and the results illustrate the proposed method is feasible to improve SET speed. Next, the R-I performances of the discrete PCM device and the resistance distributions of a 64 M bits PCM test chip with and without the initialization have been studied and analyzed, which confirms that the writing speed has been greatly improved. At the same time, the resistance distribution for the repeated initialization operations suggest that a large number of PCM cells have been successfully changed to be in an intermediate state, which is thought that only a shorter current pulse can make the cells SET successfully in this case. Compared the transmission electron microscope (TEM) images before and after initialization, it is found that there are some small grains appeared after initialization, which indicates that the nucleation process of GST has been carried out, and only needs to provide energy for grain growth later.

Orthogonal frequency division multiplexing (OFDM) technique has been widely used in communication systems in pursuit of the most efficient utilization of spectrum. However, the increase of the number of orthogonal subcarriers will lead to the rise of the peak-to-average power ratio (PAPR) of the waveform, thus reducing the efficiency of the power amplifiers. In this letter we propose a phase-changed PAPR reduction technique based on windowing function architecture for OFDM systems. This technique is based on the idea of phase change, which makes the spectrum of output signal almost free of regrowth caused by peak clipping. It can reduce more than 28dBc adjacent channel power ratio (ACPR) compared with the traditional peak windowing clipping methods in situation that peak is maximally suppressed. This technique also has low algorithm complexity so it can be easily laid out on hardware. The proposed algorithm has been laid out on a low-cost field-programmable gate array (FPGA) to verify its effectiveness and feasibility. A 64-QAM modulated 20M LTE-A waveform is used for measurement, which has a sampling rate of 245.67M.

The write operations on emerging Non-Volatile Memory (NVM), such as NAND Flash and Phase Change Memory (PCM), usually incur high access latency, and are required to be optimized. In this paper, we propose Asymmetric Read-Write (ARW) policies to minimize the write traffic sent to NVM. ARW policies exploit the asymmetry costs of read and write operations, and make adjustments on the insertion policy and hit-promotion policy of the replacement algorithm. ARW can reduce the write traffic to NVM by preventing dirty data blocks from frequent evictions. We evaluate ARW policies on systems with PCM as main memory and NAND Flash as disk. Simulation results on an 8-core multicore show that ARW adopted on the last-level cache (LLC) can reduce write traffic by more than 15% on average compared to LRU baseline. When used on both LLC and DRAM cache, ARW policies achieve an impressive reduction of 40% in write traffic without system performance degradation. When employed on the on-disk buffer of the Solid State Drive (SSD), ARW demonstrates significant reductions in both write traffic and overall access latency. Moreover, ARW policies are lightweight, easy to implement, and incur negligible storage and runtime overhead.

In this paper, we propose an optimum access method for a phase change memory (PCM) with NAND strings. A PCM with a block erase interface is proposed. The method, which has a SET block erase operation and fast RESET programming, is proposed since the SET operation causes a slow access time for conventional PCM;. From the results of measurement, the SET-ERASE operation is successfully completed while the RESET-ERASE operation is incomplete owing to serial connection. As a result, the block erase interface with the SET-ERASE and RESET program method realizes a 7.7 times faster write speed compared than a conventional RAM interface owing to the long SET time. We also give pass-transistor design guidelines for PCM with NAND strings. In addition, the write-capability and write-disturb problems are investigated. The ERASE operation for the proposed device structure can be realized with the same current as that for the SET operation of a single cell. For the pass transistor, about 4.4 times larger on-current is needed to carry out the RESET operation and to avoid the write-disturb problem than the minimum RESET current of a single cell. In this paper, the SET programming method is also verified for a conventional RAM interface. The experimental results show that the write-capability and write-disturb problems are negligible.

This paper gives a write voltage and read reference current generator considering temperature characteristics for multi-level Ge2Sb2Te5-based phase change memories. Since the optimum SET and RESET voltages linearly changes by the temperature, the voltage supply circuit must track this characteristic. In addition, the measurement results show that the read current depends on both read temperature and the write temperature and has exponential dependence on the read temperature. Thus, the binning technique is applied for each read and write temperature regions. The proposed variable TC generator can achieve below ±0.5 LSB precision from the measured differential non-linearity and integral non-linearity. As a result, the temperature characteristics of both the linear write voltage and the exponential read current can be tracked with the proposed variation tolerant linear temperature coefficient current generator.

We report a fast single element nonvolatile memory that employs amorphous to crystalline phase change. Temperature change is induced within a single electronic element in confined geometry transistors to cause the phase change. This novel phase change memory (PCM) operates without the need for charge transport through insulator films for charge storage in a floating gate. GeSbTe (GST) was employed to the phase change material undergoing transition below 200. The phase change, causing conductivity and permittivity change of the film, results in the threshold voltage shift observed in transistors and capacitors.

A novel multiple programming method for a phase change nonvolatile random access memory (NVRAM) is proposed. The resistance of the chalcogenide semiconductors (phase change materials, e.g. SeSbTe) stacked on the memory cell is controlled by the number of the applied current pulses, and we have observed experimentally 4-valued resistance in the range of 42 k-2.1kΩ at the SeSbTe discrete memory cell. On the basis of this experimental results, the 4-valued memory circuit was designed with CMOS 0.35 µm process. It has been confirmed with a circuit simulation that the multi-bit read circuit proposed works successfully under a read cycle operation over 100 MHz at 3.3 V supply voltage and the read operation is completed within 3 nsec.

We have integrated a phase change random access memory (PRAM), completely based on 0.24 µm-CMOS technologies using nitrogen doped GeSbTe films. The Ge2Sb2Te5 (GST) thin films are well known to play a critical role in writing current of PRAM. Through device simulation, we found that high-resistive GST is indispensable to minimize the writing current of PRAM. For the first time, we found the resistivity of GST film can be controlled with nitrogen doping. Doping nitrogen to GST film successfully reduced writing current. A 0.24 µm PRAM using N-doped GST films were demonstrated with writing pulse of 0.8 mA-50 ns for RESET and 0.4 mA-100 ns for SET. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen. Endurance performance of fully integrated PRAM using N-doped GST shows no fail bit up to 2E9 cycles. Allowing 1% failures, extrapolation to 85 indicates retention time of 2 years. All the results show that PRAM is one of the most promising candidates in the market for the next generation memories.