An output voltage-current equation of charge pump DC-DC voltage multiplier using diodes is provided to cover wide clock frequency and output current ranges for designing energy harvester operating at a near-threshold voltage or in sub-threshold region. Equivalent circuits in slow and fast switching limits are extracted. The effective threshold voltage of the diode in slow switching limit is also derived as a function of electrical characteristics of the diodes, such as the saturation current and voltage slope parameter, and design parameters such as the number of stages, capacitance per stage, parasitic capacitance at the top plate of the main boosting capacitor, and the clock frequency. The model is verified compared with SPICE simulation.

As is well known in the design of transformer isolated converters, the transformer leakage inductance causes a large voltage overshoot on the secondary side switching nodes at every switch transition, unless measures are taken to limit the peak voltage stress. Since the peak voltage stress in smart-power integrated converters, where the power devices are integrated on the same die as the controlling logic and supporting circuits, is the major determining factor for the required silicon area for the implementation, this is a major roadblock for the affordable integration of this type of converter. Therefore, any cost-effective smart-power synchronous rectifier requires a voltage clamping circuit that minimizes the voltage stress, while still maintaining the potential advantages of smart-power converters, i.e. minimizing the number and size of the discrete components in the converter. We present an integrated asynchronous active clamping circuit, that can clamp the overshoot voltage to arbitrary voltages while optimizing the efficiency by only being active when required. Because of the asynchronous operation, the size of the required external components is minimized. Measurements on the smart-power IC implementation of the asynchronous active clamp circuit combined with a secondary side synchronous rectifier for a 1 MHz full bridge converter confirm the reduction in voltage stress and the optimization of the efficiency.

In this paper, a wide input range CMOS multi-mode active rectifier is presented for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the mode of the multi-mode rectifier is automatically selected by switches among the original rectifier mode, 1-stage voltage multiplier mode, and 2-stage voltage multiplier mode. In the original rectifier, the range of the rectified output DC voltage is from 9 V to 19 V for an input AC voltage from 10 V to 20 V. In the multi-mode rectifier, the input-range is wider compared to the original rectifier by 5 V. As a result, the rectified output DC voltage ranges from 7.5 V to 19 V for an input AC voltage from 5 V to 20 V. The proposed multi-mode rectifier is fabricated in a 0.35 µm CMOS process with an active area of around 2500 µm 1750 µm. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency is about 94%.

Low drop-out regulators (LDOs) are widely used in the system-on-a-chip (SoC) design. Due to the multi-function and energy saving requirements for mobile applications nowadays, more strict specifications are expected on the developmental roadmap of the LDOs. An output-capacitorless LDO providing fast transient response under the low supply voltage and low quiescent current conditions is proposed in this paper. Provided by the low supply voltage, the proposed LDO adopts cascading technique using the Multipath Nested Miller Compensation (MNMC) to maintain a higher bandwidth for fast transient requirement. In addition, a Transient Quiescent Current Booster (TQCB) is supplemented to the operational amplifier to improve the slew rate for the fast load transient. The TQCB only raises the quiescent current during the load transient instant so that both power saving and the load response improvement could be well achieved. It deserves noting that the proposed TQCB contains only two transistors, which is simple to be implemented compared to the other transient current enhancement techniques. The designed LDO has only 1.6 pF capacitance for the totally added on-chip compensation, and 25.8 µA of current consumption in the main amplifier. The recovery time under the fast load change is less than 3 µs and the stability is guaranteed. Test results from the real implementation of a 0.35 µm CMOS process verify that the designed LDO performs as expected.

This paper investigates the effect of several frequency modulation profiles on conducted-noise reduction in dc-dc converters with programmed switching controller. The converter is operated in variable frequency modulation regime. Twelve switching frequency modulation profiles have been studied. Some of the modulation data are prepared using MATLAB software, and others are generated online. Moreover, all the frequency profiles have been designed and implemented using FPGA and experimentally investigated. The experimental results show that the conducted-noise spreading depends on both the modulation sequence profile and the statistical characteristics of the sequence. A substantial part of the manufacturing cost of power converters for telecommunication applications involves designing filters to comply with the EMI limits. Considering this investigation significantly reduces the filter size.

A high-efficiency CMOS rectifier circuit for UHF RFID applications was developed. The rectifier utilizes a self-Vth-cancellation (SVC) scheme in which the threshold voltage of MOSFETs is cancelled by applying gate bias voltage generated from the output voltage of the rectifier itself. A very simple circuit configuration and zero power dissipation characteristics in biasing enable excellent power conversion efficiency (PCE), especially under small RF input power conditions. At higher RF input power conditions, the PCE of the rectifier automatically decreases. This is the built-in self-power-regulation function. The proposed SVC CMOS rectifier was fabricated with a 0.35-µm CMOS process and the measured performance was compared with those of conventional nMOS, pMOS, and CMOS rectifiers and other types of Vth cancellation rectifiers as well. The SVC CMOS rectifier achieves 32% of PCE at the -10 dBm RF input power condition. This PCE is larger than rectifiers reported to date under this condition.

The reduction of undesired electromagnetic emissions in switched power converters is a hot topic. Here, we propose a chaos based methodology to synthesize PWM-like signals for controlling the drives of induction motors. This approach reduces drastically the interference due to the drive-motor ensemble, and does not significantly alter the motor performance. The benefit is a 20 dB reduction in the peak of the emitted power density spectrum. This result is herein confirmed three times: first with an analytical approach based on approximations whose impact is progressively reduced; then by means of simulation; finally by laboratory testing of a working prototype.

In this paper, a novel technique using proportional current feedback is proposed to improve dynamic response of digital PWM DC-DC converters. Generally, digital controllers are implemented using microprocessors or DSPs. Additional A/D converters are required to sense feedback signals. Proposed simple structure makes it feasible to integrate both A/D converter and digital controller on a single chip. System complexity and hardware cost are therefore greatly reduced. A behavioral time domain circuit model is proposed and analyzed using MATLAB. Both simulation and experimental results showed satisfactory performance to meet power requirements of microprocessors.

This paper describes an efficient simulation approach of a DSP controlled series-parallel resonant high frequency DC-DC power converter system. Proposed power conversion circuit simulation approach is based on a circuit equation, modeled by substituting time-varying switched resistor circuit in place of all the controllable and uncontrollable power semiconductor switching blocks of power converter circuits. An algebraic algorithm transforms the matrices of the circuit equation into the matrices of the state vector equation. Solution of state equation is by 3rd order Runge Kutta numerical integration method. Simulation results are illustrated and discussed together with experimental results.