In this paper, we propose a projection based design of near perfect reconstruction QMF banks. An advantage of this method is that additional design specifications are easily implemented by defining new convex sets. To apply convex projection technique, the main difficulty is how to approximate the design specifications by some closed convex sets. In this paper, introducing a notion of Magnitude Product Space where a pair of magnitude responses of analysis filters is expressed as a point, we approximate design requirements of QMF banks by multiple closed convex sets in this space. The proposed method iteratively applies a convex projection technique, Hybrid Steepest Descent Method, to find a point corresponding to the optimal analysis filters at each stage, where the closed convex sets are dynamically improved. Design examples show that the proposed design method leads to significant improvement over conventional design methods.

HRTFs (head-related transfer functions) are available for sound field reproduction with spatial fidelity, since HRTFs involve the acoustic cues such as interaural time difference, interaural intensity difference and spectral cues that are used for the perception of the location of a sound image. Generally, FIR filters are used in the simulation of HRTFs. However, this method is not useful for a simply system, since the orders of the FIR filters are high. In this paper, we propose a method using IIR filter for simply realization of sound image localization. The HRTFs of a dummy-head were approximated by the following filters: (A) fourth to seventh-order IIR filters and (B) third-order IIR filters. In total, the HRTFs of 24 different directions on the horizontal plane were used as the target characteristics. Sound localization experiments for the direction and the elevation angle of a sound image were carried out for 3 subjects in a soundproof chamber. The binaural signal sounds using the HRTFs simulated by FIR filters and approximated by IIR filters (A) and (B) were reproduced via two loudspeakers, and sound image localization on the horizontal plane was realized. As the result of the experiments, the sound image localization using the HRTFs approximated by IIR filters (A) is the same accuracy as the case of using the FIR filters. This result shows that it is possible to create sound fields with binaural reproduction more simply.

High accuracy, high reliability, and high performance have to be simultaneously satisfied to achieve high productivity of the latest processing equipment. High flexibility is also required because many options are available and processing equipment is modified frequently. A high-assurance-system (HAS) model for processing equipment has been developed according to the concept of an Autonomous Decentralized System (ADS). Heterogeneous devices, that have same function and diverse qualities, are utilized to assure the different requirements of high accuracy, high reliability, and high performance simultaneously. The Data Property (DP) and Assurance Manager (AM) are proposed in this model. Different accuracy, reliability, and performance indices characterize each device, and the DP describes the differences of the properties of the data transmitted from these heterogeneous devices. The AM assures not only high reliability but also high performance and high accuracy by utilizing the heterogeneity of data described by the DP. The HAS model was applied to a device-level system used in processing equipment, and its effectiveness was verified by simulating a pressure-control system.

System level diagnosis that can identify the faulty units in the system was introduced by Preparata, Metze, and Chien. In this area, the fundamental problem is to decide the diagnosability of given networks. We study the diagnosability of networks represented by the cartesian product. Our result is the optimal one with respect to the restriction of degrees of vertices of graphs that represent the networks.

Graph products have important role in constructing many useful networks. It is known that there are four basic graph products. Properties of each product have been studied individually. We propose a unified approach to these products based on the distance in graphs, and new two products on graphs. The viewpoint of products based on the distance introduced here provides a family of products that includes almost known graph products as extremal ones and suggests new products. Also,we study relations among these six products. Finally, we investigate several classes of graph products in those context.

Simple computation method of soft value, that is used in iterative soft decision decoding, is proposed. For the product code composed of BCH(63, 57) and that composed of BCH(63, 45), computation time with the proposed method is 1/15-1/6 as that with a method based on the Chase algorithm. Bit error rate (BER) performance with the proposed method is within 0.8 [dB] inferior to that with the method based on the Chase algorithm at BER=10-5.

In order to lead an ongoing software project to success, it is important to flexibly control its dynamically-changing software process. However, it is generally impossible not only to exactly pre-define the production process but also to prescribe the process change process (meta-process). To solve the problem, we have focused on communication between the project staff through which process change requests presented by individuals can be immediately shared, designed, verified, validated and implemented. This paper proposes a communication model which can represent a wide variety of communication states between the project manager and developers discussing how to implement process change requests. The communication model has been derived by investigating the sort of process change requests and, based on the model, we have implemented a cooperative process planning system (called CooPs). CooPs is a communication environment designed for software projects and supports information sharing for discussing the process change requests. By using CooPs, the software project can flexibly deal with not only expected change requests but also unexpected ones. To evaluate the applicability of the communication model and the capabilities of CooPs, we have conducted an experiment which is an application of CooPs to the ISPW6 example problem. This paper describes the concepts of CooPs, the system implementation, and the experiment.

High-speed collision detection is important to realize a highly-safe intelligent vehicle. In collision detection, high-computational power is required to perform matching operation between discrete points on surfaces of a vehicle and obstacles in real-world environment. To achieve the highest performance, a hierarchical matching scheme is proposed based on two representations: the coarse representation and the fine representation. A vehicle is represented as a set of rectangular solids in the fine representation (fine rectangular solids), and the coarse representation, which is also a set of rectangular solids, is produced by enlarging the fine representation. If collision occurs between an obstacle discrete point and a rectangular solid in the coarse representation (coarse rectangular solid), then it is sufficient to check the only fine rectangular solids contained in the coarse one. Consequently, checks for the other fine rectangular solids can be omitted. To perform the hierarchical matching operation in parallel, a hierarchically-content-addressable memory (HCAM) is proposed. Since there is no need to perform matching operation in parallel with fine rectangular solids contained in different coarse ones, the fine ones are mapped onto a matching unit. As a result, the number of matching units can be reduced without decreasing the performance. Under the condition of the same execution time, the area of the HCAM is reduced to 46.4% in comparison with that of the conventional CAM in which the hierarchical matching scheme is not used.

This paper shows the best operators for sum-of-products expressions. We first describe conditions of functions for product and sum operations. We examine all two-variable functions and select those that meet the conditions and then evaluate the number of product terms needed in the minimum sum-of-products expressions when each combination of selected product and sum functions is used. As a result of this, we obtain three product functions and nine sum functions on three-valued logic. We show that each of three product functions can express the same functions and MODSUM function is the most suitable for reduction of product terms. Moreover, we show that similar results are obtained on four-valued logic.

The effect of lot size change and test processing logistics on VLSI manufacturing final test process efficiency and cost due to the transition of from conventional 5 or 6 inches to 300 mm (12 inches) in wafer size is evaluated through simulation analysis. Simulated results show that a high test efficiency and a low test cost are maintained regardless of arrival lot size in the range of the number of 300 mm wafers per lot from 1 to 25 and the content of express lots in the range of up to 50% by using WEIGHT+RPM rule and the right final test processing logistics. WEIGHT+RPM rule is the rule that considers the jig and temperature exchanging time, the lot waiting time in queue and also the remaining processing time of the machine in use. The logistics has a small processing and moving lot size equal to the batch size of testing equipment.

we evaluate the effect of express lots on production dispatching rule scheduling and cost in VLSI manufacturing final test process. In the assignment of express lots, we make comparisons of two rules, First In First Out (FIFO) rule which is widely used and WEIGHT+RPM rule which considers the time required for jig and temperature exchanges, the remaining processing time of the machine in use and the lot waiting time in queue. When using FIFO rule, the test efficiency begins to deteriorate and the test cost per chip begins to increase, if the content of express lots exceeds 15%. Furthermore, for 30% of express lots' content, the number of total processed lots decreases by 19% and the test cost per chip increases by 22% in comparison to the cases including no express lots. For WEIGHT+RPM rule, however, the test efficiency does not deteriorate and the test cost per chip does not increase even if the content of express lots is increased up to 50%. When we use WEIGHT+RPM rule, Express Lots Tolerances (ELTs), defined as the maximum content of express lots which permits the deterioration of the system characteristics by 5%, are about three times as high as ones when using FIFO rule. It is also found that WEIGHT+RPM rule maintains higher ELTs against the changes in the numbers of planned chips and prepared jigs as compared with FIFO rule.

The disk allocation problem examined in this paper is finding a method to distribute a Binary Cartesian Product File on multiple disks to maximize parallel disk I/O accesses for partial match retrieval. This problem is known to be NP-hard, and heuristic approaches have been applied to obtain suboptimal solutions. Recently, efficient methods such as Binary Disk Modulo (BDM) and Error Correcting Code (ECC) methods have been proposed along with the restrictions that the number of disks in which files are stored should be a power of 2. In this paper, a new Disk Allocation method based on Genetic Algorithm (DAGA) is proposed. The DAGA does not place restrictions on the number of disks to be applied and it can allocate the disks adaptively by taking into account the data access patterns. Using the schema theory, it is proven that the DAGA can realize a near-optimal solution with high probability. Comparing the quality of solution derived by the DAGA with the General Disk Modulo (GDM), BDM, and ECC methods through the simulation, shows that 1) the DAGA is superior to the GDM method in all the cases and 2) with the restrictions being placed on the number of disks, the average response time of the DAGA is always less than that of the BDM method and greater than that of the ECC method in the absence of data skew and 3) when data skew is considered, the DAGA performs better than or equal to both BDM and ECC methods, even when restrictions on the number of disks are enforced.

This paper discusses a new form of network database access with mobile agent technology, where many small database servers are distributed geographically, and are accessed through dial-up network on-demand. Coined "scattered database access" here, it enables such interesting ways of data access as asynchronous, circulatory, and the-more-you-spend-the-more-you-get kind of access. Databases to be accessed are relational databases, possibly from many different vendors, and PDM databases, also from several vendors. Relational databases, or RDBs, can be accessed by the SQL, an international standard that allows the interoperability of different RDB products in general. On the other hand, PDM databases, the data-stores for Product Data Management software, are not as inter-operable as RDBs, since the product-specific set of APIs has to be used to access them. An SQL-like language and a parser framework have been introduced to solve this problem. By implementing the parser as an object-oriented framework, the workload to adapt to many PDM products has been greatly reduced. The design and preliminary implementation has been carried out in a government-sponsored CALS project in Japan, and has been proven viable in the field, where a large steel-making company gathering information from many subordinate companies around the steel plant, and from other steel companies and equipment manufacturers.

The productivity of developing software for switching systems and the effects of using advanced software development methods were evaluated and analyzed. Productivity was found to be improved by using automatic code generation, simulator debugging, a hierarchical object-oriented software structure, and software-development-support tools. The evaluation showed that the total productivity was improved by about 20%, compared with a case where these efforts were not introduced. It also showed each effect of these methods and tools by evaluating their manpower saving ratios. These results are expected to benefit the development of various types of communication-switching and multimedia service systems. Also, our development-support tools and methods are expected to be the basis for attaining higher software development productivity.

In this paper, an algorithm for Boolean factoring is presented. The algorithm is based on a technique of rectangle covering. A distinctive feature of the algorithm is that no minimization step is required to achieve Boolean factoring. The method for computing Boolean products rests on the concepts of super-product, extended kernel and extended co-kernel-cube matrix. Results of a comparison with the algorithms GOOD_FACTOR and QUICK_FACTOR implemented in SIS are presented. SIS is a program for logic synthesis developed at the University of Berkeley. All performed tests indicate that the proposed algorithm realizes a good tradeoff between factoring quality and computing time.

In this paper an algorithm for numerical investigation of the transmission line having a generalized polygonal cross-section and open interface is proposed. Solution of the eigenmode problem is based on the method called the domain product technique, which employs a Mathieu function expansion and provides an efficient technique to the analysis of the structures with multiangular boundaries. An agreement at the obtained numerical results with existing data confirms the applicability of the theoretical analysis given in the paper.

In this paper, we introduce a Shared Multiple Rooted XOR-based Decomposition Diagram (XORDD) to represent functions with multiple outputs. Based on the XORDD representation, we develop a synthesis algorithm for general Exclusive Sum-of-Product forms (ESOP). By iteratively applying transformations and reductions, we obtain a compact XORDD which gives a minimized ESOP. Our method can synthesize larger circuits than previously possible. The compact ESOP representation provides a form that is easier to synthesize for XOR heavy multi-level circuits, such as arithmetic functions. We have applied our synthesis techniques to a large set of benchmark circuits in both PLA and combinational formats. Results of the minimized ESOP forms obtained from our synthesis algorithm are also compared to the SOP forms generated by ESPRESSO. Among the 74 circuits we have experimented with, the minimized ESOP's have fewer product terms than those of SOP's in 39 circuits.

This paper describes cellular spaces (or cellular automata) with capabilities of parallel self-reproduction and of parallel universal simulation of other cellular spaces. It is shown that there is a 1-dimensional cellular space U, called a parallel universal simulator, that can simulate any given 1-dimensional cellular space S in the sense that if an initial configuration of U has a coded information of both the local function and an initial configuration of S, then U has the same computation result that S has and the computation time of U is proportional to that of S. Two models of nontrivial parallel self-reproduction are also shown. One model is based on "state-exchange" method, and the other is based on a fixed point program of the parallel universal simulator.

Ordered Binary Decision Diagrams (OBDDs) are graph-based representations of Boolean functions which are widely used because of their good properties. In this paper, we introduce nondeterministic OBDDs (NOBDDs) and their restricted forms, and evaluate their expressive power. In some applications of OBDDs, canonicity, which is one of the good properties of OBDDs, is not necessary. In such cases, we can reduce the required amount of storage by using OBDDs in some non-canonical form. A class of NOBDDs can be used as a non-canonical form of OBDDs. In this paper, we focus on two particular methods which can be regarded as using restricted forms of NOBDDs. Our aim is to show how the size of OBDDs can be reduced in such forms from theoretical point of view. Firstly, we consider a method to solve satisfiability problem of combinational circuits using the structure of circuits as a key to reduce the NOBDD size. We show that the NOBDD size is related to the cutwidth of circuits. Secondly, we analyze methods that use OBDDs to represent Boolean functions as sets of product terms. We show that the class of functions treated feasibly in this representation strictly contains that in OBDDs and contained by that in NOBDDs.

This paper proposes a new AFC (automatic frequency control) circuit employing a double-product type frequency discriminator to enable fast acquisition in very-low CNR (carrier to noise power ratio) environments. The frequency step responses of the proposed AFC circuit are theoretically analyzed. In addition this paper evaluates the performance of the proposed AFC circuit by computer simulation in very-low CNR environments. The simulation results confirm that click noise at the frequency discriminator causes large frequency tracking error and that this error can be improved by increasing the delay time of the double-product type frequency discriminator. The frequency error can be also reduced by introducing the proposed frequency discriminator to modify the frequency error detection performance. The acquisition time of the proposed AFC circuit can be reduced by about 100 symbols compared to the conventional cross-product type AFC circuit.