The polymer matrix for the number of N in-puts/outputs, N stages and 2x2-switches is denoted as the 1-D Spanke-Benes (SB) network. Throughout the paper, the 1-D SB-network, which equals the diamond cellular array, is extended to arbitrary dimensions by a mathematical transformation (a 1-D network provides the interconnection of 1-D data). This transformation determines the multistage architecture completely by providing size, location, geometry and wiring of the switches as well as it preserves properties of the networks, e.g., the capability of sorting. The SB-networks of dimension 3 are analysed and sorting is applied.

A graph G is called an n-channel graph at vertex r if there are n independent spanning trees rooted at r. A graph G is called an n-channel graph if G is an n-channel graph at every vertex. Independent spanning trees of a graph play an important role in fault-tolerant broadcasting in the graph. In this paper we show that if G1 is an n1-channel graph and G2 is an n2-channel graph, then G1G2 is an (n1 + n2)-channel graph. We prove this fact by a construction of n1+n2 independent spanning trees of G1G2 from n1 independent spanning trees of G1 and n2 independent spanning trees of G2. As an application we describe a fault-tolerant broadcasting scheme along independent spanning trees.

Because the match phase in OPS5-type production systems requires most of the system's execution time and memory accesses, we proposed hash-based parallel production systems, CPPS (Clustered Parallel Production Systems), based on the RETE algorithm for distributed memory parallel computers, or multicomputers to reduce such a bottleneck. CPPS was effective in speeding up the match phase, but still left room for optimizations. In this paper, we introduce software cache techniques to memory nodes in the CPPS as one of the optimizations, and implement it on a multicomputer, nCUBE2. The benchmark results show that the CPPS with the software cache is about 2-fold faster than the original, and more than 7-fold faster than the simple hash method proposed by Acharya et al. for a large scale problem. The speed-up can be attributed to decreased communication costs.

In order to produce high quality multimedia contents efficiently, DTPP -desktop program production system- has been proposed. The DTPP is capable of supporting all the necessary procedures of program production, from planning to broadcasting, by molding each process into the desktop environment of program producers. The DTPP system consists of multimedia terminals, a media server, a computing server, and network system. In the DTPP, new technological concepts such as cooperative program production, indexing and utilization of attribute information of images, and video components and spatio-temporal editing will be installed.

This paper discusses the design of a small sensing device for EMI measurement which has equivalent characteristics to the absorbing clamp method, and reports the results on evaluation of the device. The device can be applied to the inspection apparatus for products such as power tools to examine conformance to EMI regulations of electromagnetic radiation spectrum. For reducing the scale of the EMI inspection apparatus, new matching circuit being replaced with the absorbing clamp method is adopted in the sensing device. Length of the sensing device is smaller than one twelfth of a wavelength of the measuring frequency in order to regard the sensing device as a concentrated constant circuit. The matching circuit is a resonant circuit which consists of a coaxial coupled transformer and a variable capacitor, and the transformer is a spiral copper tube in which a pair of AC power line wires passes. Resonant frequency of the circuit is tuned to the measuring frequency by adjusting the variable capacitor so that the circuit would terminate the power line by impedance zero. Thus interference current propagating along the power line from a product is absorbed, and observed by means of a VHF current probe which is settled in the matching circuit. A simple circuit for measurement of noise amplitude distribution (NAD) of interference current was developed as well as an equation to estimate quasi-peak value from the NAD. Result of measurement by the sensing device and proposed procedure confirmed good correlation with the standard absorbing clamp method, and deviation was within 3dB. Measurement time was reduced to 25 s per product, and the in-line EMI checker with new sensing device can be employed in a mass production line.

This paper describes Kleenean coefficients that are a subset of Kleenean functions for use in representing multiple-valued logic functions. A conventional multiple-valued sum-of-products expression uses product terms that are the MIN of literals and constants. In this paper, a new sum-of-products expression is allowed to sum product terms that also include variables and complements of variables. Since the conventional sum-of-products expression is complete, so also is the augmented one. A minimization method of the new expression is described besed on the binary Quine-McCluskey algorithm. The result of computer simulation shows that a saving of the number of implicants used in minimal expressions by approximately 9% on the average can be obtained for some random functions. A result for some arithmetic functions shows that the minimal solutions of MOD radix SUM, MAX and MIN functions require much fewer implicants than those of the standard sum-of-products expressions. Thus, this paper clarifies that the new expression has an advantage to reduce the number of implicants in minimal sum-of-products expressions.

In arithmetic units multiplication is a very important operation. It is a common approach to use the modified Booth's algorithm to reduce the number of partial products in a multiplication and speed it up. In this letter we show two circuits that fuse the usually separate functions of generating the partial products and selecting them. The circuits designed in DPL (Double Pass-transistor Logic) are bigger in MOS transistors, but are faster and, function at higher frequencies than a typical CMOS implementation. One of our circuits also has lower power consumption.

This paper presents Ternary Decision Diagrams which represent sets of products. This paper also presents manipulating methods for sum-of-products forms and ringsum-of-products forms using Ternary Decision Diagrams, and gives comparison results between Ternary Decision Diagrams and Binary Decision Diagrams.

This paper describes, from a system architectural viewpoint, how knowledge-based technologies have been utilized in developing EXLOG (an LSI circuit synthesis system) and SOFTEX (a software synthesis system) inside the authors' projects. Although the system architectures for EXLOG and SOFTEX started from the same production systems, consisting of transformation rules in the middle of the 1980's, both branched off in different directions in the 1990's. Based on experiences with EXLOG and SOFTEX, the differences between LSI and software design models are discussed, and the future directions are indicated for the knowledge-based design system architectures.

The purpose of this research is to analyze production rules with coupling modes in active databases and to exploit an assistant system for rule programming. Each production rule is a specification including an event, a condition, and an action. The action is automatically executed whenever the event occurs and the condition is satisfied. Coupling modes are useful to control execution order of transactions. For example, a transaction for consistency check should be executed after transactions for update. An active database, which is a database with production rules, can spontaneously update database states and check their consistency. Production rules provide a powerful mechanism for knowledge-bases. However it is very difficult in general to predict how a set of production rules will behave because of cascading rule triggers, concurrency, and so on. We are attempting to adopt a process algebra as a basic tool to analyze production rules. In order to describe and analyze concurrent and communicating systems, process algebras such as CCS, CSP, ACP, and π-calculus, are well known. However there are some difficulties to apply existing process algebras to analysis of production rules in growing process trees by process creation. In this paper we propose a process algebra named CCSPR (a Calculus of Communicating Systems with Production Rules), Which is an extension of CCS. An advantage of CCSPR is to syntactically describe growing process trees. Therefore, production rules can be appropriately analyzed in CCSPR. After giving definitions and properties of CCSPR, we show an example of analysis of production rules in CCSPR.

This paper surveys low-power circuit techniques for CMOS ULSIs. For many years a power supply voltage of 5 V was employed. During this period power dissipation of CMOS ICs as a whole increased four-fold every three years. It is predicted that by the year 2000 the power dissipation of high-end ICs will exceed the practical limits of ceramic packages, even if the supply voltage can be feasibly reduced. CMOS ULSIs now face a power dissipation crisis. A new philosophy of circuit design is required. The power dissipation can be minimized by reducing: 1) supply voltage, 2) load capacitance, or 3) switching activity. Reducing the supply voltage brings a quadratic improvement in power dissipation. This simple solution, however, comes at a cost in processing speed. We investigate the proposed methods of compensating for the increased delay at low voltage. Reducing the load capacitance is the principal area of interest because it contributes to the improvement of both power dissipation and circuit speed. Pass-transistor logic is attracting attention as it requires fewer transistors and exhibits less stray capacitance than conventional CMOS static cicuits. Variations in its circuit topology as well as a logic synthesis method are presented and studied. A great deal of research effort has been directed towards studying every portion of LSI circuits. The research achievements are categorized in this paper by parameters associated with the source of CMOS power dissipation and power use in a chip.

Throughout the paper, the nearest-neighbour (NN) interconnection of switches within a multistage interconnection network (MIN) is analysed. Three main results are obtained: (1) The switch preserving transformation of a 2-D MIN into the 1-D MIN (and vice versa) (2) The rearrangeability of the MIN and (3) The number of stages (NS) for the rearrangeable nonblocking interconnection. The analysis is extended to any dimension of the interconnected data set. The topological equivalence between 1-D MINs with NN interconnections (NN-MINs) and 1-D cellular arrays is shown.

This paper shows that a convolution property holds for sixteen members of a sinusoidal unitary transform family (DCTs and DSTs), on condition that an impulse response is an even function. Instead of the periodicity of an input signal assumed in the DFT case, DCTs require the input signal to be even symmetric outside boundaries and DSTs require it to be odd symmetric. The property is obtained by solving the eigenvalue problem of the matrices representing the convolution. The content of the property is that the DCT (or the DST) element of the output signal is the product of the DCT (or the DST) element of the input signal and the DFT element of the impulse response. The result for the well-known DCT is useful for a strongly-correlated signal and two examples demonstrate it.

We discuss estimation error as a basic problem in formant estimation in the analysis of speech of very short-time duration in the glottal closure of the vowel. We also show in our simulation that good estimation of the first formant is almost impossible with the ordinary method using a waveform cutting. We propose a new method in which the cut waveform, as a discontinuous function of finite time, is mapped to a continuous function defined in the whole time domain; and we show that using this method, the estimation accuracy for low frequency formants can be greatly improved.

We develop a convergence theory of the simple genetic algorithm (SGA) for two-bit problems (Type I TBP and Type II TBP). SGA consists of two operations, reproduction and crossover. These are imitations of selection and recombination in biological systems. TBP is the simplest optimization problem that is devised with an intention to deceive SGA into deviating from the maximum point. It has been believed that, empirically, SGA can deviate from the maximum point for Type II while it always converges to the maximum point for Type I. Our convergence theory is a first mathematical achievement to ensure that the belief is true. Specifically, we demonstrate the following. (a) SGA always converges to the maximum point for Type I, starting from any initial point. (b) SGA converges either to the maximum or second maximum point for Type II, depending upon its initial points. Regarding Type II, we furthermore elucidate a typical sufficient initial condition under which SGA converges either to the maximum or second maximum point. Consequently, our convergence theory establishes a solid foundation for more general GA convergence theory that is in its initial stage of research. Moreover, it can bring powerful analytical techniques back to the research of original biological systems.

In this letter, we present a distinct alternative of cross talk formulation of associative memory based on the outer product algorithm extended to the higher order and a performance evaluation in terms of the probability of exact data recall by using this formulation. The significant feature of these formulations is that both cross talk and the probability formulated are explicitly represented as the functional forms of Hamming distance between the memorized keys and the applied input key, and the degree of higher order correlation. Simulation results show that exact data retrieval ability of the associative memory using randomly generated data and keys is in well agreement with our theoretical estimation.

This paper deals with the size of switching functions in Exclusive-OR sum-of-products expressions (ESOPs). The size is the number of products in ESOP. There are no good algorithms to find an exact minimum ESOP. Since the exact minimization algorithms take a time in double exponential order, it is almost impossible to minimize ESOPs for an arbitrary n-variable functions with n5. Then,it is necessary to study the size of some concrete functions. These concrete functions are useful for testing heuristic minimization algorithms. In this paper we present the lower bounds on size of periodic functions in ESOPs. A symmetric function is said to be periodic when the vector of weights of inputs X such that f(X)1 is periodic. We show that the size of a 2t+1-periodic function with rank r is proportional to n2t+r, where t0 and 0r2t, i.e., in polynomial order,and thet the size of a (2s+1)2t-periodic function with s0 and t0 is greater than or equal to (3/2)n-(2s+1)2t, i.e., in exponential order. The concrete function the size of which is greater than or equal to 32(3/2)n-8 is presented. This function requires the largest size among the concrete functions the sizes of which are known. Some results for non-periodic symmetric functions are also given.

This letter presents an algorithm named SPM which generates test patterns for single stuck-at faults in synchronous sequential circuits based on a product machine traversal method. The new idea presented in this letter is partitioned image computation combined with a mixed breadth-first/depth-first search. Image computation is carried out in partitioned manner by substituting constant logical values to some input variables. This brings about significant reduction in storage requirement during image computation. A test generator based on SPM achieved 100% fault efficiency for the ISCAS'89 benchmark circuits with not more than 32 flip-flops.

In this paper we propose an architecture and an algorithm for the parallel execution of OPS5 production systems. It is known that current OPS5 production system interpreters spend almost 90% of their execution time in the match step. Thus, in this paper we focus on the speedup of the match step. The match algorithm used in OPS5 is called Rete and the algorithm uses a special kind of a date-flow network compiled from the left hand sides of rules. To achieve the maximum degree of parallelism of a given OPS5 program by as few processors as possible, the proposed parallel machine uses loosely coupled multiprocessors. Parallel machines designed for fine-grain parallelism, such as DADO, also use loosely coupled multiprocessors. However, the proposed machine differs from such machines at the following points: use of powerful processors which have large amounts of memories and small cycle times; use of a shared Rete network (parallel machines designed for fine-grain parallelism use an unshared Rete network); high hardware utilization. Basic ideas of the proposed parallel machine are as follows. (1) Use of a modified Rete network in which node sharing is used only for constant-test nodes and each memory node is lumped with the child two-input node. (2) Static allocation of the nodes of the modified Rete network onto processors. (3) Partition of the set of processors into three subsets: constant-test node processors, two-input node processors and conflict-set processors. (4) Use of a ring network for the interconnection network among two-input node processors. In addition to an architecture for parallel execution of OPS5 production systems, we propose a scheme for mapping the modified Rete network into the proposed architecture. The results of simulation experiments showed that the proposed architecture is promising for parallel execution of OPS5 production systems.

The matrix whose eigenvectors are the basis vectors of the DCT is introduced. This matrix leads to a convolution-product property using the DCT. Based on the property, the parameter of uniform blur, such as motion blur or out-of-focus blur, is estimated from the local minima of the DCT energy spectrum of a blurred image. Computer experiments confirmed that the DCT is superior to the DFT for estimating the parameter.