This letter presents a practical approach for high-quality built-in test using a test pattern generator called neighborhood pattern generator (NPG). NPG is practical mainly because its structure is independent of circuit under test and it can realize high fault coverage not only for stuck-at faults but also for transition faults. Some techniques are also proposed for further improvement in practical applicability of NPG. Experimental results for large industrial circuits illustrate the efficiency of the proposed approach.

Reseeding technique is proposed to improve the fault coverage in pseudo-random testing. However most of previous works on reseeding is based on storing the seeds in an external tester or in a ROM. In this paper we present a built-in reseeding technique for LFSR-based test pattern generation. The proposed structure can run both in pseudorandom mode and in reseeding mode. Besides, our method requires no storage for the seeds since in reseeding mode the seeds can be generated automatically in hardware. In this paper we also propose an efficient grouping algorithm based on simulated annealing to optimize test vector grouping. Experimental results for benchmark circuits indicate the superiority of our technique against other reseeding methods with respect to test length and area overhead. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other techniques proposed so far.

This paper presents a new deterministic built-in test scheme using a neighborhood pattern generator (NPG) to guarantee complete fault efficiency with small test-data storage. The NPG as a decoding logic generates both a parent pattern and deterministic child patterns within a small Hamming distance from the parent pattern. A set of test cubes is encoded as a set of seeds for the NPG. The proposed method is practically acceptable because no impact on a circuit under test is required and the design of the NPG does not require the results of test generation. We also describe an efficient seed generation method for the NPG. Experimental results for benchmark circuits demonstrate that the proposed method can significantly reduce the storage requirements when compared with other deterministic built-in test methods.