Viable techniques such as dynamic voltage scaling (DVS) provide a new design technique to balance system performance and energy saving. In this paper, we extend previous works on task assignment problems for a set of linear-pipeline tasks over a set of processors. Different from previous works, we revisit the problems with two additional system factors: deadline and energy-consumption, which are key factors in real-time and power-aware computation. We propose an O(nm2) time complexity algorithm to determine optimal task-assignment and speed-setting schemes leading to minimal energy consumption, for a given set of m real-time tasks running on n identical processors (with or without DVS supports). The same result can be extended to a restricted form of heterogeneous processor model. Meanwhile, we show that on homogeneous processor model more efficient algorithms can be applied and result in time complexity of O(m2) when m ≤ n. For completeness, we also discuss cases without contiguity constraints. We show under such cases the problems become at least as hard as NP-hard.

In this letter, an analytic model for real-time flow connections in a Wireless Mobile Internet (WMI) is developed, and then performance measures are derived. Some examples are also presented in order to show the call-blocking ratio and the number of connections admitted into a WMI.

Network emulation system constructs a virtual network environment which has the characteristics of controllable and repeatable network conditions. This makes it possible to predict the correctness and performance of proposed new technology before deploying to Internet. In this paper we present a methodology for evaluating the correctness and performance of applications based on the PARNEM, a parallel discrete event network emulator. PARNEM employs a BSP based real-time event scheduling engine, provides flexible interactive mechanism and facilitates legacy network models reuse. PARNEM allows detailed and accurate study of application behavior. Comprehensive case studies covering bottleneck bandwidth measurement and distributed cooperative web caching system demonstrate that network emulation technology opens a wide range of new opportunities for examining the behavior of applications.

In this paper a new approach for employing the digital signal processing capabilities in the design of the multi-bit continuous time (CT) Delta Sigma modulators (DSM's) is presented. It proposes the discrete time (DT) pre-filtering before the DAC for solving the known problems of the CT DSM's.

This letter proves the finish time predictability of EDZL (Earliest Deadline Zero Laxity) scheduling algorithm for multiprocessor real-time systems, which is a variant of EDF. Based on the results, it also shows that EDZL can successfully schedule any periodic task set if its total utilization is not greater than (m+1)/2, where m is the number of processors.

3G must offer high data rates since it should support real-time multimedia services; one performance enhancement, the use of the OVSF code tree, has adopted in 3G WCDMA networks. Unfortunately, this technique allows the link capacity to be set at the base rate times powers of two. This results in wasting bandwidth while the required rate is not powers of two of the basic rate. Several multi-code assignment mechanisms have been proposed to reduce the waste rate, but incur some drawbacks, including high complexity of handling multiple codes and increasing cost of using more rake combiners. Our solution is a dynamic grouping code assignment that allows any rate to be achieved with a single code for any possible rate of traffic. The dynamic grouping approach first forms several calls into a group. It then allocates a subtree to the group and dynamically shares the subtree codes based on time-sharing of slots within a group cycle time. The waste rate and code blocking is thus reduced significantly. Since transmission delay and jitter may occur in such a time-sharing approach, two schemes of cycle interleaving are proposed to minimize delay and jitter. Numerical results demonstrate that the proposed approach reduces the waste rate and increases the system utilization obviously, and the proposed cycle interleaving schemes minimizes delay and jitter significantly.

In 2004, Tsuji and Shimizu proposed a one-time password authentication protocol, named 2GR (Two-Gene-Relation password authentication protocol). The design goal of the 2GR protocol is to eliminate the stolen-verifier attack on SAS-2 (Simple And Secure password authentication protocol, ver.2) and the theft attack on ROSI (RObust and SImple password authentication protocol). Tsuji and Shimizu claimed that in the 2GR an attacker who has stolen the verifiers from the server cannot impersonate a legitimate user. This paper, however, will point out that the 2GR protocol is still vulnerable to an impersonation attack, in which any attacker can, without stealing the verifiers, masquerade as a legitimate user.

In real-time multimedia processing systems a very large part of the power consumption is due to the data storage and data transfer. Moreover, the area cost is often largely dominated by the memory modules. In deriving an optimized (for area and/or power) memory architecture, memory size computation is an important step in the exploration of the possible algorithmic specifications of multimedia applications. This paper presents a novel non-scalar approach for computing exactly the memory size in real-time multimedia algorithms. This methodology uses both algebraic techniques specific to the data-flow analysis used in modern compilers and, also, more recent advances in the theory of polyhedra. In contrast with all the previous works which are only estimation methods, this approach performs exact memory computations even for applications significantly large in terms of the code size, number of scalars, and number of array references.

To apply network monitoring functions to emerging high-quality video streaming services, we proposed an application-coexistent monitor (APCM). In APCM, a streaming server can works as an active monitor and a passive monitor. In addition, IP packets sent from the server carry monitoring information together with application's data such as video signals. To achieve APCM on a 10-Gbps network, we developed a network interface card for an application-coexistent wire-rate network monitor (AWING NIC). It provides (1) a function to append GPS-based accurate timestamps to every packet that streaming applications send and receive, which can be used for real-time monitoring of delays and inter-packet gap, and (2) functions to capture and generate 10-Gbps wire-rate traffic without depending on packets' size, achieved by our highly-efficient DMA-transfer mechanisms. Such monitoring capability are unprecedented in existing PC-based systems because of the limitation in PC system's architecture. As an evaluation of APCM in an actual network, we conducted an experiment to transmit a 6-Gbps high-quality video stream over an IP network with the system in which we installed the AWING NIC. The results revealed that the video stream became highly bursty by passing through the network, and the observed smallest inter-packet gap corresponds to the value of 10-Gbps wire-rate traffic, which supports the effectiveness of our development.

Software defined radio, which uses reconfigurable signal processing devices, requires the determination of multiple unknown parameters to realize the potential capabilities of adaptive communication. Evolutional algorithms are optimal multi dimensional search techniques, and are well known to be effective for parameter determination. This letter proposes an evolutional algorithm for learning the mobile time-varying channel parameters without any specific assumption of scattering distribution. The proposed method is very simple to realize, but can provide precise channel estimation results. Simulations of an OFDM system show that for an example of OFDM communication under the time-varying fading channel, the proposed learning method can achieve the better BER performance.

A multiple-input multiple-output software defined radio (MIMO-SDR) platform was developed for implementation of MIMO transmission and propagation measurement systems. This platform consists of multiple functional boards for baseband (BB) digital signal processing and frequency conversion of 5 GHz-band radio frequency (RF) signals. The BB boards have capability of arbitrary system implementation by rewriting software on reconfigurable devices such as field programmable gate arrays (FPGAs) and digital signal processors (DSPs). The MIMO-SDR platform employs hybrid implementation architecture by taking advantages of FPGA, DSP, and CPU, where functional blocks with the needs for real-time processing are implemented on the FPGAs/DSPs, and other blocks are processed off-line on the CPU. In order to realize the hybrid implementation, driver software was developed as an application program interface (API) of the MIMO-SDR platform. In this paper, hardware architecture of the developed MIMO-SDR platform and its software implementation architecture are explained. As an application example, implementation of a real-time MIMO channel measurement system and initial measurement results are presented.

A multiple-places reservation discipline is studied in a discrete-time priority queueing system. We obtain the joint distribution of system state, from which the delays of high and low priority packets are derived. Comparison is made with the cases of FIFO, single-place reservation discipline and HOL priority.

This letter proposed a linear precoding scheme for the V-BLAST system that requires only knowledge of the statistical CSI; the transmitter does not need the instantaneous CSI. Power allocation on the eigenmodes of the transmit correlation matrix is one way to minimize bit error rate (BER). Simulation results show that the proposed precoding V-BLAST system provides a significant reduction in the BER compared with the conventional V-BLAST systems.

In this paper, a multiuser receiver based on a Gaussian Mixture Sigma Point Particle Filter (GMSPPF), which can be used for joint channel coefficient estimation and time delay tracking in CDMA communication systems, is introduced. The proposed algorithm has better improved estimation performance than either Extended Kalman Filter (EKF) or Particle Filter (PF). The Cramer-Rao Lower Bound (CRLB) is derived for the estimator, and the simulation result demonstrates that it is almost completely near-far resistant. For this reason, it is believed that the proposed estimator can replace well-known filters such as the EKF or PF.

A NULL-convention circuit based on dual-rail current-mode differential logic is proposed for a high-performance asynchronous VLSI. Since input/output signals are mapped to dual-rail current signals, the NULL-convention circuit can be directly implemented based on the dual-rail differential logic, which results in the reduction of the device counts. As a typical example, a NULL-convention logic based full adder using the proposed circuit is implemented by a 0.18 µm CMOS technology. Its delay, power dissipation and area are reduced to 61 percent, 60 percent and 62 percent, respectively, in comparison with those of a corresponding CMOS implementation.

Multiple-input multiple-output (MIMO) systems using eigenbeam space division multiplexing (E-SDM) perform well and have increased capacities compared with those using conventional space division multiplexing (SDM). However, channel state information (CSI) is required at a transmitter, and the performance of E-SDM systems depends much on the accuracy of the CSI at a transmitter and a receiver. In time-varying fading environments, the channel change between the transmit weight determination time and the actual data transmission time causes the system performance to degrade. To compensate for the channel error, a linear extrapolation method has been proposed for a time division duplexing system. Unfortunately, the system performance still deteriorates as the maximum Doppler frequency increases. Here, two new techniques of channel extrapolation are proposed. One is second order extrapolation, and the other is exponential extrapolation. Also, we propose maximum Doppler frequency estimation methods for exponential extrapolation. Simulation results for 4tx 4rx MIMO systems showed that using the proposed techniques, E-SDM system performs better in a higher Doppler frequency region.

In computer simulation of a large number of moving objects (MOs), how to enlarge Δt (the interval between the simulation time steps) without introducing causality errors is one of the primary keys to enhancing performance. Causality errors can be avoided by using the same Δt among related MOs when they are in the scene of detection (SoD). But in a large-scale MO simulation, MOs interact with one another in a complicated manner requiring a large calculation cost to predict the beginning time of SoD. In this paper we propose an event-aware dynamic time step synchronization method (DTSS) for distributed MO simulation, which increases Δt without introducing causality errors and speeds up the simulation. DTSS can be implemented with little calculation cost because: (1) DTSS does not calculate the beginning time of SoD exactly, but calculates the time for possible entry into SoD with a simple mechanisim, and (2) MO simulation consists of a "movement"-phase and a "detection"-phase in which the distance-calculation between MOs requires a heavy load, and DTSS utilizes the distance values to calculate Δt. In this paper, we also discuss a suitable HLA based time management mechanism to implement DTSS on a distributed computing environment. In the performance evaluation of DTSS, the calculation cost of DTSS is implemented by using the HLA suitable time management mechanism. The results show that DTSS can be executed within the ideal time plus its 1% over-cost when a basic scenario of war-game simulation is employed. Therefore if the ratio of SoD to the total simulation is small, the execution time is expected to decrease to nearly this ratio. We also introduce the criterion for determining when DTSS is superior to the conventional method by using the performance evaluation results. The results presented in this paper are effectively utilized when DTSS is applied to practical applications.

The Video Quality Experts Group (VQEG) is preparing a programme of subjective multimedia quality tests. The results from these tests will be used to evaluate the performance of competing objective multimedia quality metrics. The reliability of the subjective test data is of great importance for VQEG's task. This paper provides an overview of VQEG's multimedia ad-hoc group. The work of this group will require subjective tests to be performed by laboratories located in Europe, Asia and North America. For VQEG's multimedia work to be successful, the subjective assessment methodology must be precisely defined and produce reliable and repeatable subjective quality data. Although international standards covering multimedia quality assessment methods are in force, there remains some uncertainty regarding the most effective approach to assessing the subjective quality of multimedia. A review of existing methods is provided. Two experiments are presented investigating the suitability of alternative subjective assessment methods (single-stimulus ACR and SAMVIQ). The results of these experiments are discussed within the context of the VQEG multimedia testing programme.

Diversity transmission using space-time block coding (STBC) shows a degraded performance in frequency selective fading (FSF) channel. In this paper, assuming the CSI is unknown at both transmitter and receiver while a pilot signal is available during the training period, we propose a MIMO transmission scheme using STBC by adopting subband adaptive array (SBAA) processing. The receive signal is converted into the frequency-domain and adaptive processing is done at each subband. A novel construction of SBAA is introduced to process received signal based on STBC. Simulation results demonstrate that the proposed scheme has a better performance compare to conventional STBC, and has a better performance and less computational load compare to STBC-TDLAA.

Petri nets with inhibitor arcs are referred to as inhibitor-arc Petri nets. It is shown that modeling capability of inhibitor-arc Petri nets is equivalent to that of Turing machines. The subject of this paper is the legal firing sequence problem (INLFS) for inhibitor-arc Petri nets: given an inhibitor-arc Petri net IN, an initial marking M0 and a firing count vector X, find a firing sequence δ such that its firing starts from M0 and each transition t appears in δ exactly X(t) times as prescribed by X. The paper is the first step of research for time complexity analysis and designing algorithms of INLFS, one of the most fundamental problems for inhibitor-arc Petri nets having more modeling capability than ordinary Peri nets. The recognition version of INLFS, denoted as RINLFS, means a decision problem, asking a "yes" or "no" answer on the existence of a solution δ to INLFS. The main results are the following (1) and (2). (1) Proving (1-1) and (1-2) when the underlying Petri net of IN is an unweighted state machine: (1-1) INLFS can be solved in pseudo-polynomial (O(|X|)) time for IN of non-adjacent type having only one special place called a rivet; (1-2) RINLFS is NP-hard for IN with at least three rivets; (2) Proving that RINLFS for IN whose underlying Petri net is unweighted and forward conflict-free is NP-hard. Heuristic algorithms for solving INLFS are going to be proposed in separate papers.