In this paper, an efficient one-way point-to-multipoint communication protocol (PTMP) is proposed. The PTM protocol is helpful to distribute information to many workstations simultaneously and correctly. The PTM protocol is designed for network channels with low error possibility. The PTM protocol utilizes broadcast for data distributing. Re-transmission request for lost packet is returned to the server, and acknowledgment for correctly received packets is not returned to the server. We have applied the protocol to the network presentation system. The network presentation system is intended to display same graphical images to multiple workstations simultaneously on an X window system. This presentation system is able to provide services for at least forty X servers simultaneously, the capacity is limited to X server performance, except for pixmap drawing. For the case of pixmap drawing, the system capacity is limited to the network bandwidth. To solve network bandwidth problem, we combined PTM protocol with the network presentation system. With PTM protocol, system performance is improved and the use of network bandwidth is lowered.

Synthesis tools are now extensively used in the VLSI circuit design process. They allow a much higher design productivity, but the designer often does not directly control the circuit structure. Thus, when circuits are dedicated to dependable applications, designers have difficulties in implementing manually the devices needed to obtain fault detection or tolerance capabilities. The ASYL-SdF System has been developed over the last few years in order to avoid this break in the design flow, and to facilitate the designer's work when dependability is targeted. This paper gives an overview of the resulting tool, its synthesis flow for fault detection and fault tolerance in Finite State Machines, its limitations and the current developments. Actual circuit implementation results are given in terms of area overheads, expected reliability and experimental fault detection coverage.

This paper discusses a software verification support environment Vega which is based on a model-theoretic methodology that enables verification support for the temporal properties of protocol specifications described in the formal description technique LOTOS. In the methodology of Vega, a protocol specification is defined through the LOTOS process reflecting its practical system structure. The temporal properties to be verified are given as the requirement which the protocol needs to satisfy from the viewpoint of events and are formulated by using the branching time temporal logic defined in this paper. Verification is done by determining whether or not the given temporal properties are satisfied by the model, which corresponds to the transition system derived from the LOTOS specification of the protocol. Vega is provided with an effective interface function, as well as the function of simple model checking based on the above methodology, to give some degree of flexibility for the expression of temporal properties to be verified. Specifically, it allows the user to define useful expressions by combining builtin temporal logic formulas and enter them in Vega for use at any time. With the provision of these functions, Vega is expected to serve as a very powerful and flexible verification support tool.

In the program development process, it is ofren necessary for programmers to know the differences between two programs, or two different versions of a program. Since programs have structures such as iteration statement and selection statement, applying text-based tools such as UNIX diff to identify the differences may produce unsatisfactory results. In this paper, we exploit a tree as the internal representation of a program, obtain the mapping between two trees and display the program differences visually based on the mapping and pretty-printing technique so that the structural differences can be identified immediately.

This paper proposes the concept of Tool-Based Direct Deformation Method (TB-DDM) which supports networked CAD (Computer Aided Design) systems with virtual reality technologies. TB-DDM allows designers to sculpt free forms directly with tools; each tool has its deforming characteristics, such as, the area and the shape of deformation. TB-DDM's direct deformation interface is independent of form representations because the system automatically calculates appropriate deformation according to its form representation when a tool pushes" a form. The deformation with TB-DDM is concisely described by the initial shape, types of tools, and thier loci; the description enables cooperative CAD systems with narrow bandwidth network to share design process rapidly and to distribute computational load.

Recent developments and case studies regarding VLSI device chip failure analysis are reviewed. The key failure analysis techniques reviewed include EMMS (emission microscopy), OBIC (optical beam induced current), LCM (liquid crystal method), EBP (electron beam probing), and FIB (focused ion beam method). Further, future possibilities in failure analysis, and some promising new tools are introduced.

This paper describes the current implementation and experimental results of a hardware/software codesign system for ASIP (Application Specific Integrated Processor) development： the PEAS-I System. The PEAS-I system accepts a set of application programs written in C language, associated data set, module database, and design constraints such as chip area and power consumption. The system then generates an optimized CPU core design in the form of an HDL as well as a set of application program development tools such as a C compiler, an assembler and a simulator. Another important feature of the PEAS-I system is that the system is able to give accurate estimations of chip area and performance before the detailed design of the ASIP is completed. According to the experimental results, the PEAS-I system has been found to be highly effective and efficient for ASIP development.

We have developed an advanced tool for dimensioning circuit-switched networks, called CNEP (Circuit-Switched Network Evaluation Program) , for effective design of digital networks. CNEP features a high-reliability network structure (node dispersion, double homing, etc) , both-way circuit operation, and circuit modularity (or big module size), all of which are critical for digital networks. CNEP also solves other dimensioning problems such as the cost difference between existing and newly installed circuits, and handles multi-hour traffic conditions, dynamic routing, and multiple-switching-unit nodes. Operations Research techniques are applied to produce exact and heuristic algorithms for these problems. Algorithms with good time-performance trade-off characteristics are chosen for CNEP.