IEICE TRANSACTIONS on Electronics
A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme
Summary :
A CMOS wireless transceiver operating in the 14-18 GHz range is proposed. The receiver uses direct conversion architecture for demodulation with a fast carrier and symbol timing recovery scheme. The transmitter uses a PLL and an up-conversion mixer to generate BPSK modulated signal. A ring oscillator is used in the PLL to make faster switching for burst transmission obtaining high speed low power operation. The transceiver operation has been verified by system simulation while the transmitter test-chip was fabricated in 65 nm CMOS technology and verified with measured results. The transmitter generates a bi-phase modulated signal with a center frequency of 16 GHz at a maximum data rate of 4 Gb/s and consumes 61 mW of power. To the best knowledge of authors, this is lowest power consumption among the reported transmitters that operate over 1 Gb/s range. The transceiver is proposed for a target communication distance of 10 cm.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.1 pp.120-127
- Publication Date
- 2010/01/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.120
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
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Keyword
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Vishal V. KULKARNI, Hiroki ISHIKURO, Tadahiro KURODA, "A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 1, pp. 120-127, January 2010, doi: 10.1587/transele.E93.C.120.
Abstract: A CMOS wireless transceiver operating in the 14-18 GHz range is proposed. The receiver uses direct conversion architecture for demodulation with a fast carrier and symbol timing recovery scheme. The transmitter uses a PLL and an up-conversion mixer to generate BPSK modulated signal. A ring oscillator is used in the PLL to make faster switching for burst transmission obtaining high speed low power operation. The transceiver operation has been verified by system simulation while the transmitter test-chip was fabricated in 65 nm CMOS technology and verified with measured results. The transmitter generates a bi-phase modulated signal with a center frequency of 16 GHz at a maximum data rate of 4 Gb/s and consumes 61 mW of power. To the best knowledge of authors, this is lowest power consumption among the reported transmitters that operate over 1 Gb/s range. The transceiver is proposed for a target communication distance of 10 cm.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.120/_p
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@ARTICLE{e93-c_1_120,
author={Vishal V. KULKARNI, Hiroki ISHIKURO, Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme},
year={2010},
volume={E93-C},
number={1},
pages={120-127},
abstract={A CMOS wireless transceiver operating in the 14-18 GHz range is proposed. The receiver uses direct conversion architecture for demodulation with a fast carrier and symbol timing recovery scheme. The transmitter uses a PLL and an up-conversion mixer to generate BPSK modulated signal. A ring oscillator is used in the PLL to make faster switching for burst transmission obtaining high speed low power operation. The transceiver operation has been verified by system simulation while the transmitter test-chip was fabricated in 65 nm CMOS technology and verified with measured results. The transmitter generates a bi-phase modulated signal with a center frequency of 16 GHz at a maximum data rate of 4 Gb/s and consumes 61 mW of power. To the best knowledge of authors, this is lowest power consumption among the reported transmitters that operate over 1 Gb/s range. The transceiver is proposed for a target communication distance of 10 cm.},
keywords={},
doi={10.1587/transele.E93.C.120},
ISSN={1745-1353},
month={January},}
Copy
TY - JOUR
TI - A 4-Gbps Quasi-Millimeter-Wave Transmitter in 65 nm CMOS and a Fast Carrier and Symbol Timing Recovery Scheme
T2 - IEICE TRANSACTIONS on Electronics
SP - 120
EP - 127
AU - Vishal V. KULKARNI
AU - Hiroki ISHIKURO
AU - Tadahiro KURODA
PY - 2010
DO - 10.1587/transele.E93.C.120
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2010
AB - A CMOS wireless transceiver operating in the 14-18 GHz range is proposed. The receiver uses direct conversion architecture for demodulation with a fast carrier and symbol timing recovery scheme. The transmitter uses a PLL and an up-conversion mixer to generate BPSK modulated signal. A ring oscillator is used in the PLL to make faster switching for burst transmission obtaining high speed low power operation. The transceiver operation has been verified by system simulation while the transmitter test-chip was fabricated in 65 nm CMOS technology and verified with measured results. The transmitter generates a bi-phase modulated signal with a center frequency of 16 GHz at a maximum data rate of 4 Gb/s and consumes 61 mW of power. To the best knowledge of authors, this is lowest power consumption among the reported transmitters that operate over 1 Gb/s range. The transceiver is proposed for a target communication distance of 10 cm.
ER -
English
