A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS
Summary :
This paper presents an analog front-end circuit for a 60-GHz proximity wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224mW Power consumption.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E98-A No.2 pp.492-499
- Publication Date
- 2015/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E98.A.492
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
Masanori FURUTA
Toshiba Corporation
Hidenori OKUNI
Toshiba Corporation
Masahiro HOSOYA
Toshiba Corporation
Akihide SAI
Toshiba Corporation
Junya MATSUNO
Toshiba Corporation
Shigehito SAIGUSA
Toshiba Corporation
Tetsuro ITAKURA
Toshiba Corporation
Keyword
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Masanori FURUTA, Hidenori OKUNI, Masahiro HOSOYA, Akihide SAI, Junya MATSUNO, Shigehito SAIGUSA, Tetsuro ITAKURA, "A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS" in IEICE TRANSACTIONS on Fundamentals,
vol. E98-A, no. 2, pp. 492-499, February 2015, doi: 10.1587/transfun.E98.A.492.
Abstract: This paper presents an analog front-end circuit for a 60-GHz proximity wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224mW Power consumption.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E98.A.492/_p
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@ARTICLE{e98-a_2_492,
author={Masanori FURUTA, Hidenori OKUNI, Masahiro HOSOYA, Akihide SAI, Junya MATSUNO, Shigehito SAIGUSA, Tetsuro ITAKURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS},
year={2015},
volume={E98-A},
number={2},
pages={492-499},
abstract={This paper presents an analog front-end circuit for a 60-GHz proximity wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224mW Power consumption.},
keywords={},
doi={10.1587/transfun.E98.A.492},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 492
EP - 499
AU - Masanori FURUTA
AU - Hidenori OKUNI
AU - Masahiro HOSOYA
AU - Akihide SAI
AU - Junya MATSUNO
AU - Shigehito SAIGUSA
AU - Tetsuro ITAKURA
PY - 2015
DO - 10.1587/transfun.E98.A.492
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E98-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2015
AB - This paper presents an analog front-end circuit for a 60-GHz proximity wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224mW Power consumption.
ER -
English
