A Novel ATPG Method for Capture Power Reduction during Scan Testing
Summary :
High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive IR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness.
- Publication
- IEICE TRANSACTIONS on Information Vol.E90-D No.9 pp.1398-1405
- Publication Date
- 2007/09/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1093/ietisy/e90-d.9.1398
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Keyword
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Xiaoqing WEN, Seiji KAJIHARA, Kohei MIYASE, Tatsuya SUZUKI, Kewal K. SALUJA, Laung-Terng WANG, Kozo KINOSHITA, "A Novel ATPG Method for Capture Power Reduction during Scan Testing" in IEICE TRANSACTIONS on Information,
vol. E90-D, no. 9, pp. 1398-1405, September 2007, doi: 10.1093/ietisy/e90-d.9.1398.
Abstract: High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive IR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness.
URL: https://global.ieice.org/en_transactions/information/10.1093/ietisy/e90-d.9.1398/_p
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@ARTICLE{e90-d_9_1398,
author={Xiaoqing WEN, Seiji KAJIHARA, Kohei MIYASE, Tatsuya SUZUKI, Kewal K. SALUJA, Laung-Terng WANG, Kozo KINOSHITA, },
journal={IEICE TRANSACTIONS on Information},
title={A Novel ATPG Method for Capture Power Reduction during Scan Testing},
year={2007},
volume={E90-D},
number={9},
pages={1398-1405},
abstract={High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive IR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness.},
keywords={},
doi={10.1093/ietisy/e90-d.9.1398},
ISSN={1745-1361},
month={September},}
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TY - JOUR
TI - A Novel ATPG Method for Capture Power Reduction during Scan Testing
T2 - IEICE TRANSACTIONS on Information
SP - 1398
EP - 1405
AU - Xiaoqing WEN
AU - Seiji KAJIHARA
AU - Kohei MIYASE
AU - Tatsuya SUZUKI
AU - Kewal K. SALUJA
AU - Laung-Terng WANG
AU - Kozo KINOSHITA
PY - 2007
DO - 10.1093/ietisy/e90-d.9.1398
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E90-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2007
AB - High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive IR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness.
ER -
English
