On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST

Akihiro TOMITA; Xiaoqing WEN; Yasuo SATO; Seiji KAJIHARA; Kohei MIYASE; Stefan HOLST; Patrick GIRARD; Mohammad TEHRANIPOOR; Laung-Terng WANG

doi:10.1587/transinf.2014EDP7039

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST

Akihiro TOMITA, Xiaoqing WEN, Yasuo SATO, Seiji KAJIHARA, Kohei MIYASE, Stefan HOLST, Patrick GIRARD, Mohammad TEHRANIPOOR, Laung-Terng WANG

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The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses even for good circuits. Different from conventional low-power BIST, this paper is the first to explicitly focus on achieving capture power safety with a novel and practical scheme, called capture-power-safe logic BIST (CPS-LBIST). The basic idea is to identify all possibly-erroneous test responses caused by excessive capture power and use the well-known approach of masking (bit-masking, slice-masking,vector-masking) to block them from reaching the multiple-input signature register(MISR). Experiments with large benchmark circuits and a large industrial circuit demonstrate that CPS-LBIST can achieve capture power safety with negligible impact on test quality and circuit overhead.

Publication: IEICE TRANSACTIONS on Information Vol.E97-D No.10 pp.2706-2718

Publication Date: 2014/10/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.2014EDP7039

Type of Manuscript: PAPER

Category: Dependable Computing

Authors

Akihiro TOMITA
  Kyushu Institute of Technology
Xiaoqing WEN
  Kyushu Institute of Technology
Yasuo SATO
  Kyushu Institute of Technology
Seiji KAJIHARA
  Kyushu Institute of Technology
Kohei MIYASE
  Kyushu Institute of Technology
Stefan HOLST
  Kyushu Institute of Technology
Patrick GIRARD
  LIRMM
Mohammad TEHRANIPOOR
  University of Connecticut
Laung-Terng WANG
  SynTest Technologies, Inc.

Keyword

at-speed scan-based logic BIST, capture power safety, masking, IR-drop, transition delay fault, long sensitized path

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Akihiro TOMITA, Xiaoqing WEN, Yasuo SATO, Seiji KAJIHARA, Kohei MIYASE, Stefan HOLST, Patrick GIRARD, Mohammad TEHRANIPOOR, Laung-Terng WANG, "On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST" in IEICE TRANSACTIONS on Information, vol. E97-D, no. 10, pp. 2706-2718, October 2014, doi: 10.1587/transinf.2014EDP7039.
Abstract: The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses even for good circuits. Different from conventional low-power BIST, this paper is the first to explicitly focus on achieving capture power safety with a novel and practical scheme, called capture-power-safe logic BIST (CPS-LBIST). The basic idea is to identify all possibly-erroneous test responses caused by excessive capture power and use the well-known approach of masking (bit-masking, slice-masking,vector-masking) to block them from reaching the multiple-input signature register(MISR). Experiments with large benchmark circuits and a large industrial circuit demonstrate that CPS-LBIST can achieve capture power safety with negligible impact on test quality and circuit overhead.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2014EDP7039/_p

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@ARTICLE{e97-d_10_2706,
author={Akihiro TOMITA, Xiaoqing WEN, Yasuo SATO, Seiji KAJIHARA, Kohei MIYASE, Stefan HOLST, Patrick GIRARD, Mohammad TEHRANIPOOR, Laung-Terng WANG, },
journal={IEICE TRANSACTIONS on Information},
title={On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST},
year={2014},
volume={E97-D},
number={10},
pages={2706-2718},
abstract={The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses even for good circuits. Different from conventional low-power BIST, this paper is the first to explicitly focus on achieving capture power safety with a novel and practical scheme, called capture-power-safe logic BIST (CPS-LBIST). The basic idea is to identify all possibly-erroneous test responses caused by excessive capture power and use the well-known approach of masking (bit-masking, slice-masking,vector-masking) to block them from reaching the multiple-input signature register(MISR). Experiments with large benchmark circuits and a large industrial circuit demonstrate that CPS-LBIST can achieve capture power safety with negligible impact on test quality and circuit overhead.},
keywords={},
doi={10.1587/transinf.2014EDP7039},
ISSN={1745-1361},
month={October},}

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TY - JOUR
TI - On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST
T2 - IEICE TRANSACTIONS on Information
SP - 2706
EP - 2718
AU - Akihiro TOMITA
AU - Xiaoqing WEN
AU - Yasuo SATO
AU - Seiji KAJIHARA
AU - Kohei MIYASE
AU - Stefan HOLST
AU - Patrick GIRARD
AU - Mohammad TEHRANIPOOR
AU - Laung-Terng WANG
PY - 2014
DO - 10.1587/transinf.2014EDP7039
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E97-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2014
AB - The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses even for good circuits. Different from conventional low-power BIST, this paper is the first to explicitly focus on achieving capture power safety with a novel and practical scheme, called capture-power-safe logic BIST (CPS-LBIST). The basic idea is to identify all possibly-erroneous test responses caused by excessive capture power and use the well-known approach of masking (bit-masking, slice-masking,vector-masking) to block them from reaching the multiple-input signature register(MISR). Experiments with large benchmark circuits and a large industrial circuit demonstrate that CPS-LBIST can achieve capture power safety with negligible impact on test quality and circuit overhead.
ER -